target/linux/realtek/dts-5.15/rtl839x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include <dt-bindings/clock/rtl83xx-clk.h>
   4
   5 /dts-v1/;
   6
   7 #define STRINGIZE(s) #s
   8 #define LAN_LABEL(p, s) STRINGIZE(p ## s)
   9 #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
  10
  11 #define INTERNAL_PHY(n) \
  12         phy##n: ethernet-phy@##n { \
  13                 reg = <##n>; \
  14                 compatible = "ethernet-phy-ieee802.3-c22"; \
  15                 phy-is-integrated; \
  16         };
  17
  18 #define EXTERNAL_PHY(n) \
  19         phy##n: ethernet-phy@##n { \
  20                 reg = <##n>; \
  21                 compatible = "ethernet-phy-ieee802.3-c22"; \
  22         };
  23
  24 #define EXTERNAL_SFP_PHY(n) \
  25         phy##n: ethernet-phy@##n { \
  26                 compatible = "ethernet-phy-ieee802.3-c22"; \
  27                 sfp; \
  28                 media = "fibre"; \
  29                 reg = <##n>; \
  30         };
  31
  32 #define EXTERNAL_SFP_PHY_FULL(n, s) \
  33         phy##n: ethernet-phy@##n { \
  34                 compatible = "ethernet-phy-ieee802.3-c22"; \
  35                 sfp = <&sfp##s>; \
  36                 reg = <##n>; \
  37         };
  38
  39 #define SWITCH_PORT(n, s, m) \
  40         port@##n { \
  41                 reg = <##n>; \
  42                 label = SWITCH_PORT_LABEL(s) ; \
  43                 phy-handle = <&phy##n>; \
  44                 phy-mode = #m ; \
  45         };
  46
  47 #define SWITCH_SFP_PORT(n, s, m) \
  48         port@##n { \
  49                 reg = <##n>; \
  50                 label = SWITCH_PORT_LABEL(s) ; \
  51                 phy-handle = <&phy##n>; \
  52                 phy-mode = #m ; \
  53                 fixed-link { \
  54                         speed = <1000>; \
  55                         full-duplex; \
  56                 }; \
  57         };
  58
  59 / {
  60         #address-cells = <1>;
  61         #size-cells = <1>;
  62
  63         compatible = "realtek,rtl839x-soc";
  64
  65         osc: oscillator {
  66                 compatible = "fixed-clock";
  67                 #clock-cells = <0>;
  68                 clock-frequency = <25000000>;
  69         };
  70
  71         ccu: clock-controller {
  72                 compatible = "realtek,rtl8390-clock";
  73                 #clock-cells = <1>;
  74                 clocks = <&osc>;
  75                 clock-names = "ref_clk";
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu@0 {
  83                         compatible = "mips,mips34Kc";
  84                         reg = <0>;
  85                         clocks = <&ccu CLK_CPU>;
  86                         operating-points-v2 = <&cpu_opp_table>;
  87                 };
  88
  89                 cpu@1 {
  90                         compatible = "mips,mips34Kc";
  91                         reg = <1>;
  92                         clocks = <&ccu CLK_CPU>;
  93                         operating-points-v2 = <&cpu_opp_table>;
  94                 };
  95         };
  96
  97         cpu_opp_table: opp-table-0 {
  98                 compatible = "operating-points-v2";
  99                 opp-shared;
 100
 101                 opp00 {
 102                         opp-hz = /bits/ 64 <425000000>;
 103                 };
 104                 opp01 {
 105                         opp-hz = /bits/ 64 <450000000>;
 106                 };
 107                 opp02 {
 108                         opp-hz = /bits/ 64 <475000000>;
 109                 };
 110                 opp03 {
 111                         opp-hz = /bits/ 64 <500000000>;
 112                 };
 113                 opp04 {
 114                         opp-hz = /bits/ 64 <525000000>;
 115                 };
 116                 opp05 {
 117                         opp-hz = /bits/ 64 <550000000>;
 118                 };
 119                 opp06 {
 120                         opp-hz = /bits/ 64 <575000000>;
 121                 };
 122                 opp07 {
 123                         opp-hz = /bits/ 64 <600000000>;
 124                 };
 125                 opp08 {
 126                         opp-hz = /bits/ 64 <625000000>;
 127                 };
 128                 opp09 {
 129                         opp-hz = /bits/ 64 <650000000>;
 130                 };
 131                 opp10 {
 132                         opp-hz = /bits/ 64 <675000000>;
 133                 };
 134                 opp11 {
 135                         opp-hz = /bits/ 64 <700000000>;
 136                 };
 137                 opp12 {
 138                         opp-hz = /bits/ 64 <725000000>;
 139                 };
 140                 opp13 {
 141                         opp-hz = /bits/ 64 <750000000>;
 142                 };
 143         };
 144
 145         aliases {
 146                 serial0 = &uart0;
 147                 serial1 = &uart1;
 148         };
 149
 150         chosen {
 151                 bootargs = "earlycon";
 152                 stdout-path = "serial0:115200n8";
 153         };
 154
 155         cpuintc: cpuintc {
 156                 compatible = "mti,cpu-interrupt-controller";
 157                 #address-cells = <0>;
 158                 #interrupt-cells = <1>;
 159                 interrupt-controller;
 160         };
 161
 162         soc: soc {
 163                 compatible = "simple-bus";
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166                 ranges = <0x0 0x18000000 0x10000>;
 167
 168                 intc: interrupt-controller@3000 {
 169                         compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
 170                         reg = <0x3000 0x18>, <0x3018 0x18>;
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173
 174                         interrupt-parent = <&cpuintc>;
 175                         interrupts = <2>, <3>, <4>, <5>, <6>;
 176                 };
 177
 178                 spi0: spi@1200 {
 179                         compatible = "realtek,rtl8380-spi";
 180                         reg = <0x1200 0x100>;
 181
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                 };
 185
 186                 timer0: timer@3100 {
 187                         compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
 188                         reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
 189                               <0x3130 0x10>, <0x3140 0x10>;
 190
 191                         interrupt-parent = <&intc>;
 192                         interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
 193                         clocks = <&ccu CLK_LXB>;
 194                 };
 195
 196                 uart0: uart@2000 {
 197                         compatible = "ns16550a";
 198                         reg = <0x2000 0x100>;
 199
 200                         clocks = <&ccu CLK_LXB>;
 201
 202                         interrupt-parent = <&intc>;
 203                         interrupts = <31 1>;
 204
 205                         reg-io-width = <1>;
 206                         reg-shift = <2>;
 207                         fifo-size = <1>;
 208                         no-loopback-test;
 209                 };
 210
 211                 uart1: uart@2100 {
 212                         pinctrl-names = "default";
 213                         pinctrl-0 = <&enable_uart1>;
 214
 215                         compatible = "ns16550a";
 216                         reg = <0x2100 0x100>;
 217
 218                         clocks = <&ccu CLK_LXB>;
 219
 220                         interrupt-parent = <&intc>;
 221                         interrupts = <30 2>;
 222
 223                         reg-io-width = <1>;
 224                         reg-shift = <2>;
 225                         fifo-size = <1>;
 226                         no-loopback-test;
 227
 228                         status = "disabled";
 229                 };
 230
 231                 gpio0: gpio-controller@3500 {
 232                         compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
 233                         reg = <0x3500 0x20>;
 234
 235                         gpio-controller;
 236                         #gpio-cells = <2>;
 237                         ngpios = <24>;
 238
 239                         interrupt-controller;
 240                         #interrupt-cells = <2>;
 241                         interrupt-parent = <&intc>;
 242                         interrupts = <23 2>;
 243                 };
 244
 245                 watchdog0: watchdog@3150 {
 246                         compatible = "realtek,rtl8390-wdt";
 247                         reg = <0x3150 0xc>;
 248
 249                         realtek,reset-mode = "soc";
 250
 251                         clocks = <&ccu CLK_LXB>;
 252                         timeout-sec = <30>;
 253
 254                         interrupt-parent = <&intc>;
 255                         interrupt-names = "phase1", "phase2";
 256                         interrupts = <19 4>, <18 4>;
 257                 };
 258
 259         };
 260
 261         pinmux@1b000004 {
 262                 compatible = "pinctrl-single";
 263                 reg = <0x1b000004 0x4>;
 264
 265                 pinctrl-single,bit-per-mux;
 266                 pinctrl-single,register-width = <32>;
 267                 pinctrl-single,function-mask = <0x1>;
 268                 #pinctrl-cells = <2>;
 269
 270                 enable_uart1: pinmux_enable_uart1 {
 271                         pinctrl-single,bits = <0x0 0x1 0x3>;
 272                 };
 273
 274                 disable_jtag: pinmux_disable_jtag {
 275                         pinctrl-single,bits = <0x0 0x2 0x3>;
 276                 };
 277         };
 278
 279         /* LED_GLB_CTRL */
 280         pinmux@1b0000e4 {
 281                 compatible = "pinctrl-single";
 282                 reg = <0x1b0000e4 0x4>;
 283
 284                 pinctrl-single,bit-per-mux;
 285                 pinctrl-single,register-width = <32>;
 286                 pinctrl-single,function-mask = <0x1>;
 287                 #pinctrl-cells = <2>;
 288
 289                 /* enable GPIO 0 */
 290                 pinmux_disable_sys_led: disable_sys_led {
 291                         pinctrl-single,bits = <0x0 0x0 0x4000>;
 292                 };
 293         };
 294
 295         ethernet0: ethernet@1b00a300 {
 296                 compatible = "realtek,rtl838x-eth";
 297                 reg = <0x1b00a300 0x100>;
 298
 299                 interrupt-parent = <&intc>;
 300                 interrupts = <24 3>;
 301
 302                 phy-mode = "internal";
 303
 304                 fixed-link {
 305                         speed = <1000>;
 306                         full-duplex;
 307                 };
 308         };
 309
 310         sram0: sram@9f000000 {
 311                 compatible = "mmio-sram";
 312                 reg = <0x9f000000 0x18000>;
 313                 #address-cells = <1>;
 314                 #size-cells = <1>;
 315                 ranges = <0 0x9f000000 0x18000>;
 316         };
 317
 318         switch0: switch@1b000000 {
 319                 status = "okay";
 320                 compatible = "realtek,rtl83xx-switch";
 321
 322                 interrupt-parent = <&intc>;
 323                 interrupts = <20 2>;
 324         };
 325 };