target/linux/realtek/dts-5.10/rtl930x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8
   9         compatible = "realtek,rtl838x-soc";
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14                 frequency = <800000000>;
  15
  16                 cpu@0 {
  17                         compatible = "mips,mips34Kc";
  18                         reg = <0>;
  19                 };
  20         };
  21
  22         memory@0 {
  23                 device_type = "memory";
  24                 reg = <0x0 0x8000000>;
  25         };
  26
  27         chosen {
  28                 bootargs = "console=ttyS0,115200";
  29         };
  30
  31         cpuintc: cpuintc {
  32                 compatible = "mti,cpu-interrupt-controller";
  33                 #address-cells = <0>;
  34                 #interrupt-cells = <1>;
  35                 interrupt-controller;
  36         };
  37
  38         lx_clk: lx_clk {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 clock-frequency  = <175000000>;
  42         };
  43
  44         soc: soc {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0x0 0x18000000 0x10000>;
  49
  50                 intc: interrupt-controller@3000 {
  51                         compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
  52                         reg = <0x3000 0x18>, <0x3018 0x18>;
  53                         interrupt-controller;
  54                         #interrupt-cells = <2>;
  55
  56                         interrupt-parent = <&cpuintc>;
  57                         interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
  58                 };
  59
  60                 rtl9300clock: rtl9300clock@3200 {
  61                         compatible = "realtek,rtl9300clock";
  62                         reg = <0xb8003200 0x10>;
  63                         #address-cells = <0>;
  64                         #interrupt-cells = <1>;
  65
  66                         interrupt-parent = <&intc>;
  67                         interrupts = <7 5>, <8 5>;
  68                 };
  69
  70                 spi0: spi@1200 {
  71                         compatible = "realtek,rtl8380-spi";
  72                         reg = <0x1200 0x100>;
  73
  74                         #address-cells = <1>;
  75                         #size-cells = <0>;
  76                 };
  77
  78                 uart0: uart@2000 {
  79                         compatible = "ns16550a";
  80                         reg = <0x2000 0x100>;
  81
  82                         clocks = <&lx_clk>;
  83
  84                         interrupt-parent = <&intc>;
  85                         interrupts = <30 1>;
  86
  87                         reg-io-width = <1>;
  88                         reg-shift = <2>;
  89                         fifo-size = <1>;
  90                         no-loopback-test;
  91                 };
  92
  93                 uart1: uart@2100 {
  94                         compatible = "ns16550a";
  95                         reg = <0x2100 0x100>;
  96
  97                         clocks = <&lx_clk>;
  98
  99                         interrupt-parent = <&intc>;
 100                         interrupts = <31 0>;
 101
 102                         reg-io-width = <1>;
 103                         reg-shift = <2>;
 104                         fifo-size = <1>;
 105                         no-loopback-test;
 106
 107                         status = "disabled";
 108                 };
 109
 110                 watchdog0: watchdog@3260 {
 111                         compatible = "realtek,rtl9300-wdt";
 112                         reg = <0x3260 0xc>;
 113
 114                         realtek,reset-mode = "soc";
 115
 116                         clocks = <&lx_clk>;
 117                         timeout-sec = <30>;
 118
 119                         interrupt-parent = <&intc>;
 120                         interrupt-names = "phase1", "phase2";
 121                         interrupts = <5 4>, <6 4>;
 122                 };
 123
 124                 gpio0: gpio-controller@3300 {
 125                         compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
 126                         reg = <0x3300 0x1c>, <0x3338 0x8>;
 127
 128                         gpio-controller;
 129                         #gpio-cells = <2>;
 130                         ngpios = <24>;
 131
 132                         interrupt-controller;
 133                         #interrupt-cells = <2>;
 134                         interrupt-parent = <&intc>;
 135                         interrupts = <13 1>;
 136                 };
 137
 138         };
 139
 140         ethernet0: ethernet@1b00a300 {
 141                 compatible = "realtek,rtl838x-eth";
 142                 reg = <0x1b00a300 0x100>;
 143
 144                 interrupt-parent = <&intc>;
 145                 interrupts = <24 3>;
 146
 147                 phy-mode = "internal";
 148
 149                 fixed-link {
 150                         speed = <1000>;
 151                         full-duplex;
 152                 };
 153         };
 154
 155         switch0: switch@1b000000 {
 156                 compatible = "realtek,rtl83xx-switch";
 157                 status = "okay";
 158
 159                 interrupt-parent = <&intc>;
 160                 interrupts = <23 2>;
 161         };
 162 };