target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts

   1 /dts-v1/;
   2
   3 #include "rtl839x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc";
  10         model = "Zyxel GS1900-48";
  11
  12         aliases {
  13                 led-boot = &led_sys;
  14                 led-failsafe = &led_sys;
  15                 led-running = &led_sys;
  16                 led-upgrade = &led_sys;
  17         };
  18
  19         memory@0 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x8000000>;
  22         };
  23
  24         chosen {
  25                 bootargs = "console=ttyS0,115200";
  26         };
  27
  28         leds {
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinmux_disable_sys_led>;
  31                 compatible = "gpio-leds";
  32
  33                 led_sys: sys {
  34                         label = "green:sys";
  35                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  36                 };
  37         };
  38
  39         gpio1: rtl8231-gpio {
  40                 compatible = "realtek,rtl8231-gpio";
  41                 #gpio-cells = <2>;
  42                 indirect-access-bus-id = <3>;
  43                 gpio-controller;
  44
  45                 status = "okay";
  46         };
  47
  48         gpio-restart {
  49                 compatible = "gpio-restart";
  50                 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  51         };
  52
  53         keys {
  54                 compatible = "gpio-keys-polled";
  55                 poll-interval = <20>;
  56
  57                 mode {
  58                         label = "reset";
  59                         gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
  60                         linux,code = <KEY_RESTART>;
  61                 };
  62         };
  63
  64         /* i2c of the left SFP cage: port 49 */
  65         i2c0: i2c-gpio-0 {
  66                 compatible = "i2c-gpio";
  67                 sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  68                 scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  69                 i2c-gpio,delay-us = <2>;
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72         };
  73
  74         sfp0: sfp-p9 {
  75                 compatible = "sff,sfp";
  76                 i2c-bus = <&i2c0>;
  77                 los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
  78                 tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
  79                 mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
  80                 tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
  81         };
  82
  83         /* i2c of the right SFP cage: port 50 */
  84         i2c1: i2c-gpio-1 {
  85                 compatible = "i2c-gpio";
  86                 sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  87                 scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  88                 i2c-gpio,delay-us = <2>;
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91         };
  92
  93         sfp1: sfp-p10 {
  94                 compatible = "sff,sfp";
  95                 i2c-bus = <&i2c1>;
  96                 los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
  97                 tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  98                 mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
  99                 tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 100         };
 101 };
 102
 103 &spi0 {
 104         status = "okay";
 105         flash@0 {
 106                 compatible = "jedec,spi-nor";
 107                 reg = <0>;
 108                 spi-max-frequency = <10000000>;
 109
 110                 partitions {
 111                         compatible = "fixed-partitions";
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114
 115                         partition@0 {
 116                                 label = "u-boot";
 117                                 reg = <0x0 0x40000>;
 118                                 read-only;
 119                         };
 120                         partition@40000 {
 121                                 label = "u-boot-env";
 122                                 reg = <0x40000 0x10000>;
 123                                 read-only;
 124                         };
 125                         partition@50000 {
 126                                 label = "u-boot-env2";
 127                                 reg = <0x50000 0x10000>;
 128                                 read-only;
 129                         };
 130                         partition@60000 {
 131                                 label = "jffs";
 132                                 reg = <0x60000 0x100000>;
 133                         };
 134                         partition@160000 {
 135                                 label = "jffs2";
 136                                 reg = <0x160000 0x100000>;
 137                         };
 138                         partition@b260000 {
 139                                 label = "firmware";
 140                                 reg = <0x260000 0xda0000>;
 141                                 compatible = "openwrt,uimage", "denx,uimage";
 142                                 openwrt,ih-magic = <0x83800000>;
 143                         };
 144                         partition@930000 {
 145                                 label = "runtime2";
 146                                 reg = <0x930000 0x6d0000>;
 147                         };
 148                 };
 149         };
 150 };
 151
 152 &ethernet0 {
 153         mdio: mdio-bus {
 154                 compatible = "realtek,rtl838x-mdio";
 155                 regmap = <&ethernet0>;
 156                 #address-cells = <1>;
 157                 #size-cells = <0>;
 158
 159                 /* External phy RTL8218B #1 */
 160                 EXTERNAL_PHY(0)
 161                 EXTERNAL_PHY(1)
 162                 EXTERNAL_PHY(2)
 163                 EXTERNAL_PHY(3)
 164                 EXTERNAL_PHY(4)
 165                 EXTERNAL_PHY(5)
 166                 EXTERNAL_PHY(6)
 167                 EXTERNAL_PHY(7)
 168
 169                 /* External phy RTL8218B #2 */
 170                 EXTERNAL_PHY(8)
 171                 EXTERNAL_PHY(9)
 172                 EXTERNAL_PHY(10)
 173                 EXTERNAL_PHY(11)
 174                 EXTERNAL_PHY(12)
 175                 EXTERNAL_PHY(13)
 176                 EXTERNAL_PHY(14)
 177                 EXTERNAL_PHY(15)
 178
 179                 /* External phy RTL8218B #3 */
 180                 EXTERNAL_PHY(16)
 181                 EXTERNAL_PHY(17)
 182                 EXTERNAL_PHY(18)
 183                 EXTERNAL_PHY(19)
 184                 EXTERNAL_PHY(20)
 185                 EXTERNAL_PHY(21)
 186                 EXTERNAL_PHY(22)
 187                 EXTERNAL_PHY(23)
 188
 189                 /* External phy RTL8218B #4 */
 190                 EXTERNAL_PHY(24)
 191                 EXTERNAL_PHY(25)
 192                 EXTERNAL_PHY(26)
 193                 EXTERNAL_PHY(27)
 194                 EXTERNAL_PHY(28)
 195                 EXTERNAL_PHY(29)
 196                 EXTERNAL_PHY(30)
 197                 EXTERNAL_PHY(31)
 198
 199                 /* External phy RTL8218B #5 */
 200                 EXTERNAL_PHY(32)
 201                 EXTERNAL_PHY(33)
 202                 EXTERNAL_PHY(34)
 203                 EXTERNAL_PHY(35)
 204                 EXTERNAL_PHY(36)
 205                 EXTERNAL_PHY(37)
 206                 EXTERNAL_PHY(38)
 207                 EXTERNAL_PHY(39)
 208
 209                 /* External phy RTL8218B #6 */
 210                 EXTERNAL_PHY(40)
 211                 EXTERNAL_PHY(41)
 212                 EXTERNAL_PHY(42)
 213                 EXTERNAL_PHY(43)
 214                 EXTERNAL_PHY(44)
 215                 EXTERNAL_PHY(45)
 216                 EXTERNAL_PHY(46)
 217                 EXTERNAL_PHY(47)
 218
 219                 /* RTL8393 Internal SerDes */
 220                 INTERNAL_PHY(48)
 221                 INTERNAL_PHY(49)
 222         };
 223 };
 224
 225 &switch0 {
 226         ports {
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229
 230                 SWITCH_PORT(0, 01, qsgmii)
 231                 SWITCH_PORT(1, 02, qsgmii)
 232                 SWITCH_PORT(2, 03, qsgmii)
 233                 SWITCH_PORT(3, 04, qsgmii)
 234                 SWITCH_PORT(4, 05, qsgmii)
 235                 SWITCH_PORT(5, 06, qsgmii)
 236                 SWITCH_PORT(6, 07, qsgmii)
 237                 SWITCH_PORT(7, 08, qsgmii)
 238
 239                 SWITCH_PORT(8, 09, qsgmii)
 240                 SWITCH_PORT(9, 10, qsgmii)
 241                 SWITCH_PORT(10, 11, qsgmii)
 242                 SWITCH_PORT(11, 12, qsgmii)
 243                 SWITCH_PORT(12, 13, qsgmii)
 244                 SWITCH_PORT(13, 14, qsgmii)
 245                 SWITCH_PORT(14, 15, qsgmii)
 246                 SWITCH_PORT(15, 16, qsgmii)
 247
 248                 SWITCH_PORT(16, 17, qsgmii)
 249                 SWITCH_PORT(17, 18, qsgmii)
 250                 SWITCH_PORT(18, 19, qsgmii)
 251                 SWITCH_PORT(19, 20, qsgmii)
 252                 SWITCH_PORT(20, 21, qsgmii)
 253                 SWITCH_PORT(21, 22, qsgmii)
 254                 SWITCH_PORT(22, 23, qsgmii)
 255                 SWITCH_PORT(23, 24, qsgmii)
 256
 257                 SWITCH_PORT(24, 25, qsgmii)
 258                 SWITCH_PORT(25, 26, qsgmii)
 259                 SWITCH_PORT(26, 27, qsgmii)
 260                 SWITCH_PORT(27, 28, qsgmii)
 261                 SWITCH_PORT(28, 29, qsgmii)
 262                 SWITCH_PORT(29, 30, qsgmii)
 263                 SWITCH_PORT(30, 31, qsgmii)
 264                 SWITCH_PORT(31, 32, qsgmii)
 265
 266                 SWITCH_PORT(32, 33, qsgmii)
 267                 SWITCH_PORT(33, 34, qsgmii)
 268                 SWITCH_PORT(34, 35, qsgmii)
 269                 SWITCH_PORT(35, 36, qsgmii)
 270                 SWITCH_PORT(36, 37, qsgmii)
 271                 SWITCH_PORT(37, 38, qsgmii)
 272                 SWITCH_PORT(38, 39, qsgmii)
 273                 SWITCH_PORT(39, 40, qsgmii)
 274
 275                 SWITCH_PORT(40, 41, qsgmii)
 276                 SWITCH_PORT(41, 42, qsgmii)
 277                 SWITCH_PORT(42, 43, qsgmii)
 278                 SWITCH_PORT(43, 44, qsgmii)
 279                 SWITCH_PORT(44, 45, qsgmii)
 280                 SWITCH_PORT(45, 46, qsgmii)
 281                 SWITCH_PORT(46, 47, qsgmii)
 282                 SWITCH_PORT(47, 48, qsgmii)
 283
 284                 /* SFP cages */
 285                 port@48 {
 286                         reg = <48>;
 287                         label = "lan49";
 288                         phy-mode = "sgmii";
 289                         phy-handle = <&phy48>;
 290                         sfp = <&sfp0>;
 291
 292                         fixed-link {
 293                                 speed = <1000>;
 294                                 full-duplex;
 295                                 pause;
 296                         };
 297
 298                 };
 299
 300                 port@49 {
 301                         reg = <49>;
 302                         label = "lan50";
 303                         phy-mode = "sgmii";
 304                         phy-handle = <&phy49>;
 305                         sfp = <&sfp1>;
 306
 307                         fixed-link {
 308                                 speed = <1000>;
 309                                 full-duplex;
 310                                 pause;
 311                         };
 312
 313                 };
 314
 315                 /* CPU-Port */
 316                 port@52 {
 317                         ethernet = <&ethernet0>;
 318                         reg = <52>;
 319                         phy-mode = "qsgmii";
 320                         fixed-link {
 321                                 speed = <1000>;
 322                                 full-duplex;
 323                         };
 324                 };
 325         };
 326 };