target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts

   1 /dts-v1/;
   2
   3 #include "rtl839x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc";
  10         model = "Zyxel GS1900-48";
  11
  12         aliases {
  13                 led-boot = &led_sys;
  14                 led-failsafe = &led_sys;
  15                 led-running = &led_sys;
  16                 led-upgrade = &led_sys;
  17         };
  18
  19         memory@0 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x8000000>;
  22         };
  23
  24         leds {
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinmux_disable_sys_led>;
  27                 compatible = "gpio-leds";
  28
  29                 led_sys: sys {
  30                         label = "green:sys";
  31                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  32                 };
  33         };
  34
  35         gpio1: rtl8231-gpio {
  36                 compatible = "realtek,rtl8231-gpio";
  37                 #gpio-cells = <2>;
  38                 indirect-access-bus-id = <3>;
  39                 gpio-controller;
  40
  41                 status = "okay";
  42         };
  43
  44         gpio-restart {
  45                 compatible = "gpio-restart";
  46                 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  47         };
  48
  49         keys {
  50                 compatible = "gpio-keys-polled";
  51                 poll-interval = <20>;
  52
  53                 mode {
  54                         label = "reset";
  55                         gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_RESTART>;
  57                 };
  58         };
  59
  60         /* i2c of the left SFP cage: port 49 */
  61         i2c0: i2c-gpio-0 {
  62                 compatible = "i2c-gpio";
  63                 sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  64                 scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  65                 i2c-gpio,delay-us = <2>;
  66                 #address-cells = <1>;
  67                 #size-cells = <0>;
  68         };
  69
  70         sfp0: sfp-p9 {
  71                 compatible = "sff,sfp";
  72                 i2c-bus = <&i2c0>;
  73                 los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
  74                 tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
  75                 mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
  76                 tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
  77         };
  78
  79         /* i2c of the right SFP cage: port 50 */
  80         i2c1: i2c-gpio-1 {
  81                 compatible = "i2c-gpio";
  82                 sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  83                 scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  84                 i2c-gpio,delay-us = <2>;
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87         };
  88
  89         sfp1: sfp-p10 {
  90                 compatible = "sff,sfp";
  91                 i2c-bus = <&i2c1>;
  92                 los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
  93                 tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  94                 mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
  95                 tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  96         };
  97 };
  98
  99 &spi0 {
 100         status = "okay";
 101         flash@0 {
 102                 compatible = "jedec,spi-nor";
 103                 reg = <0>;
 104                 spi-max-frequency = <10000000>;
 105
 106                 partitions {
 107                         compatible = "fixed-partitions";
 108                         #address-cells = <1>;
 109                         #size-cells = <1>;
 110
 111                         partition@0 {
 112                                 label = "u-boot";
 113                                 reg = <0x0 0x40000>;
 114                                 read-only;
 115                         };
 116                         partition@40000 {
 117                                 label = "u-boot-env";
 118                                 reg = <0x40000 0x10000>;
 119                                 read-only;
 120                         };
 121                         partition@50000 {
 122                                 label = "u-boot-env2";
 123                                 reg = <0x50000 0x10000>;
 124                                 read-only;
 125                         };
 126                         partition@60000 {
 127                                 label = "jffs";
 128                                 reg = <0x60000 0x100000>;
 129                         };
 130                         partition@160000 {
 131                                 label = "jffs2";
 132                                 reg = <0x160000 0x100000>;
 133                         };
 134                         partition@b260000 {
 135                                 label = "firmware";
 136                                 reg = <0x260000 0xda0000>;
 137                                 compatible = "openwrt,uimage", "denx,uimage";
 138                                 openwrt,ih-magic = <0x83800000>;
 139                         };
 140                         partition@930000 {
 141                                 label = "runtime2";
 142                                 reg = <0x930000 0x6d0000>;
 143                         };
 144                 };
 145         };
 146 };
 147
 148 &ethernet0 {
 149         mdio: mdio-bus {
 150                 compatible = "realtek,rtl838x-mdio";
 151                 regmap = <&ethernet0>;
 152                 #address-cells = <1>;
 153                 #size-cells = <0>;
 154
 155                 /* External phy RTL8218B #1 */
 156                 EXTERNAL_PHY(0)
 157                 EXTERNAL_PHY(1)
 158                 EXTERNAL_PHY(2)
 159                 EXTERNAL_PHY(3)
 160                 EXTERNAL_PHY(4)
 161                 EXTERNAL_PHY(5)
 162                 EXTERNAL_PHY(6)
 163                 EXTERNAL_PHY(7)
 164
 165                 /* External phy RTL8218B #2 */
 166                 EXTERNAL_PHY(8)
 167                 EXTERNAL_PHY(9)
 168                 EXTERNAL_PHY(10)
 169                 EXTERNAL_PHY(11)
 170                 EXTERNAL_PHY(12)
 171                 EXTERNAL_PHY(13)
 172                 EXTERNAL_PHY(14)
 173                 EXTERNAL_PHY(15)
 174
 175                 /* External phy RTL8218B #3 */
 176                 EXTERNAL_PHY(16)
 177                 EXTERNAL_PHY(17)
 178                 EXTERNAL_PHY(18)
 179                 EXTERNAL_PHY(19)
 180                 EXTERNAL_PHY(20)
 181                 EXTERNAL_PHY(21)
 182                 EXTERNAL_PHY(22)
 183                 EXTERNAL_PHY(23)
 184
 185                 /* External phy RTL8218B #4 */
 186                 EXTERNAL_PHY(24)
 187                 EXTERNAL_PHY(25)
 188                 EXTERNAL_PHY(26)
 189                 EXTERNAL_PHY(27)
 190                 EXTERNAL_PHY(28)
 191                 EXTERNAL_PHY(29)
 192                 EXTERNAL_PHY(30)
 193                 EXTERNAL_PHY(31)
 194
 195                 /* External phy RTL8218B #5 */
 196                 EXTERNAL_PHY(32)
 197                 EXTERNAL_PHY(33)
 198                 EXTERNAL_PHY(34)
 199                 EXTERNAL_PHY(35)
 200                 EXTERNAL_PHY(36)
 201                 EXTERNAL_PHY(37)
 202                 EXTERNAL_PHY(38)
 203                 EXTERNAL_PHY(39)
 204
 205                 /* External phy RTL8218B #6 */
 206                 EXTERNAL_PHY(40)
 207                 EXTERNAL_PHY(41)
 208                 EXTERNAL_PHY(42)
 209                 EXTERNAL_PHY(43)
 210                 EXTERNAL_PHY(44)
 211                 EXTERNAL_PHY(45)
 212                 EXTERNAL_PHY(46)
 213                 EXTERNAL_PHY(47)
 214
 215                 /* RTL8393 Internal SerDes */
 216                 INTERNAL_PHY(48)
 217                 INTERNAL_PHY(49)
 218         };
 219 };
 220
 221 &switch0 {
 222         ports {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225
 226                 SWITCH_PORT(0, 01, qsgmii)
 227                 SWITCH_PORT(1, 02, qsgmii)
 228                 SWITCH_PORT(2, 03, qsgmii)
 229                 SWITCH_PORT(3, 04, qsgmii)
 230                 SWITCH_PORT(4, 05, qsgmii)
 231                 SWITCH_PORT(5, 06, qsgmii)
 232                 SWITCH_PORT(6, 07, qsgmii)
 233                 SWITCH_PORT(7, 08, qsgmii)
 234
 235                 SWITCH_PORT(8, 09, qsgmii)
 236                 SWITCH_PORT(9, 10, qsgmii)
 237                 SWITCH_PORT(10, 11, qsgmii)
 238                 SWITCH_PORT(11, 12, qsgmii)
 239                 SWITCH_PORT(12, 13, qsgmii)
 240                 SWITCH_PORT(13, 14, qsgmii)
 241                 SWITCH_PORT(14, 15, qsgmii)
 242                 SWITCH_PORT(15, 16, qsgmii)
 243
 244                 SWITCH_PORT(16, 17, qsgmii)
 245                 SWITCH_PORT(17, 18, qsgmii)
 246                 SWITCH_PORT(18, 19, qsgmii)
 247                 SWITCH_PORT(19, 20, qsgmii)
 248                 SWITCH_PORT(20, 21, qsgmii)
 249                 SWITCH_PORT(21, 22, qsgmii)
 250                 SWITCH_PORT(22, 23, qsgmii)
 251                 SWITCH_PORT(23, 24, qsgmii)
 252
 253                 SWITCH_PORT(24, 25, qsgmii)
 254                 SWITCH_PORT(25, 26, qsgmii)
 255                 SWITCH_PORT(26, 27, qsgmii)
 256                 SWITCH_PORT(27, 28, qsgmii)
 257                 SWITCH_PORT(28, 29, qsgmii)
 258                 SWITCH_PORT(29, 30, qsgmii)
 259                 SWITCH_PORT(30, 31, qsgmii)
 260                 SWITCH_PORT(31, 32, qsgmii)
 261
 262                 SWITCH_PORT(32, 33, qsgmii)
 263                 SWITCH_PORT(33, 34, qsgmii)
 264                 SWITCH_PORT(34, 35, qsgmii)
 265                 SWITCH_PORT(35, 36, qsgmii)
 266                 SWITCH_PORT(36, 37, qsgmii)
 267                 SWITCH_PORT(37, 38, qsgmii)
 268                 SWITCH_PORT(38, 39, qsgmii)
 269                 SWITCH_PORT(39, 40, qsgmii)
 270
 271                 SWITCH_PORT(40, 41, qsgmii)
 272                 SWITCH_PORT(41, 42, qsgmii)
 273                 SWITCH_PORT(42, 43, qsgmii)
 274                 SWITCH_PORT(43, 44, qsgmii)
 275                 SWITCH_PORT(44, 45, qsgmii)
 276                 SWITCH_PORT(45, 46, qsgmii)
 277                 SWITCH_PORT(46, 47, qsgmii)
 278                 SWITCH_PORT(47, 48, qsgmii)
 279
 280                 /* SFP cages */
 281                 port@48 {
 282                         reg = <48>;
 283                         label = "lan49";
 284                         phy-mode = "sgmii";
 285                         phy-handle = <&phy48>;
 286                         sfp = <&sfp0>;
 287
 288                         fixed-link {
 289                                 speed = <1000>;
 290                                 full-duplex;
 291                                 pause;
 292                         };
 293
 294                 };
 295
 296                 port@49 {
 297                         reg = <49>;
 298                         label = "lan50";
 299                         phy-mode = "sgmii";
 300                         phy-handle = <&phy49>;
 301                         sfp = <&sfp1>;
 302
 303                         fixed-link {
 304                                 speed = <1000>;
 305                                 full-duplex;
 306                                 pause;
 307                         };
 308
 309                 };
 310
 311                 /* CPU-Port */
 312                 port@52 {
 313                         ethernet = <&ethernet0>;
 314                         reg = <52>;
 315                         phy-mode = "qsgmii";
 316                         fixed-link {
 317                                 speed = <1000>;
 318                                 full-duplex;
 319                         };
 320                 };
 321         };
 322 };