target/linux/realtek/dts-5.10/rtl8382_inaba_aml2-17gp.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
  10         model = "INABA Abaniact AML2-17GP";
  11
  12         chosen {
  13                 bootargs = "console=ttyS0,115200";
  14         };
  15
  16         memory@0 {
  17                 device_type = "memory";
  18                 reg = <0x0 0x8000000>;
  19         };
  20
  21         keys {
  22                 compatible = "gpio-keys";
  23
  24                 reset {
  25                         label = "reset";
  26                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  27                         linux,code = <KEY_RESTART>;
  28                 };
  29         };
  30 };
  31
  32 &spi0 {
  33         status = "okay";
  34
  35         flash@0 {
  36                 compatible = "jedec,spi-nor";
  37                 reg = <0>;
  38                 spi-max-frequency = <10000000>;
  39
  40                 partitions {
  41                         compatible = "fixed-partitions";
  42                         #address-cells = <1>;
  43                         #size-cells = <1>;
  44
  45                         partition@0 {
  46                                 label = "u-boot";
  47                                 reg = <0x0 0x80000>;
  48                                 read-only;
  49                         };
  50
  51                         partition@80000 {
  52                                 label = "u-boot-env";
  53                                 reg = <0x80000 0x10000>;
  54                                 read-only;
  55                         };
  56
  57                         partition@90000 {
  58                                 label = "u-boot-env2";
  59                                 reg = <0x90000 0x10000>;
  60                         };
  61
  62                         partition@a0000 {
  63                                 label = "jffs2_cfg";
  64                                 reg = <0xa0000 0x400000>;
  65                                 read-only;
  66                         };
  67
  68                         partition@4a0000 {
  69                                 label = "jffs2_log";
  70                                 reg = <0x4a0000 0x100000>;
  71                                 read-only;
  72                         };
  73
  74                         partition@5a0000 {
  75                                 compatible = "openwrt,uimage", "denx,uimage";
  76                                 label = "firmware";
  77                                 reg = <0x5a0000 0xd30000>;
  78                                 openwrt,ih-magic = <0x83800000>;
  79                         };
  80
  81                         partition@12d0000 {
  82                                 label = "runtime2";
  83                                 reg = <0x12d0000 0xd30000>;
  84                         };
  85                 };
  86         };
  87 };
  88
  89 &ethernet0 {
  90         mdio-bus {
  91                 compatible = "realtek,rtl838x-mdio";
  92                 regmap = <&ethernet0>;
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95
  96                 INTERNAL_PHY(8)
  97                 INTERNAL_PHY(9)
  98                 INTERNAL_PHY(10)
  99                 INTERNAL_PHY(11)
 100                 INTERNAL_PHY(12)
 101                 INTERNAL_PHY(13)
 102                 INTERNAL_PHY(14)
 103                 INTERNAL_PHY(15)
 104
 105                 EXTERNAL_PHY(16)
 106                 EXTERNAL_PHY(17)
 107                 EXTERNAL_PHY(18)
 108                 EXTERNAL_PHY(19)
 109                 EXTERNAL_PHY(20)
 110                 EXTERNAL_PHY(21)
 111                 EXTERNAL_PHY(22)
 112                 EXTERNAL_PHY(23)
 113
 114                 EXTERNAL_PHY(24)
 115         };
 116 };
 117
 118 &switch0 {
 119         ports {
 120                 #address-cells = <1>;
 121                 #size-cells = <0>;
 122
 123                 SWITCH_PORT(8, 1, internal)
 124                 SWITCH_PORT(9, 2, internal)
 125                 SWITCH_PORT(10, 3, internal)
 126                 SWITCH_PORT(11, 4, internal)
 127                 SWITCH_PORT(12, 5, internal)
 128                 SWITCH_PORT(13, 6, internal)
 129                 SWITCH_PORT(14, 7, internal)
 130                 SWITCH_PORT(15, 8, internal)
 131
 132                 SWITCH_PORT(16, 9, qsgmii)
 133                 SWITCH_PORT(17, 10, qsgmii)
 134                 SWITCH_PORT(18, 11, qsgmii)
 135                 SWITCH_PORT(19, 12, qsgmii)
 136                 SWITCH_PORT(20, 13, qsgmii)
 137                 SWITCH_PORT(21, 14, qsgmii)
 138                 SWITCH_PORT(22, 15, qsgmii)
 139                 SWITCH_PORT(23, 16, qsgmii)
 140
 141                 port@24 {
 142                         reg = <24>;
 143                         label = "wan";
 144                         phy-handle = <&phy24>;
 145                         phy-mode = "qsgmii";
 146                 };
 147
 148                 port@28 {
 149                         ethernet = <&ethernet0>;
 150                         reg = <28>;
 151                         phy-mode = "internal";
 152
 153                         fixed-link {
 154                                 speed = <1000>;
 155                                 full-duplex;
 156                         };
 157                 };
 158         };
 159 };