realtek: Consolidate bootargs
[openwrt/staging/hauke.git] / target / linux / realtek / dts-5.10 / rtl8380_zyxel_gs1900.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "rtl838x.dtsi"
4
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
7
8 / {
9 aliases {
10 led-boot = &led_sys;
11 led-failsafe = &led_sys;
12 led-running = &led_sys;
13 led-upgrade = &led_sys;
14 };
15
16 memory@0 {
17 device_type = "memory";
18 reg = <0x0 0x8000000>;
19 };
20
21 keys {
22 compatible = "gpio-keys-polled";
23 poll-interval = <20>;
24
25 reset {
26 label = "reset";
27 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
28 linux,code = <KEY_RESTART>;
29 };
30 };
31
32 leds {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinmux_disable_sys_led>;
35 compatible = "gpio-leds";
36
37 led_sys: sys {
38 label = "green:sys";
39 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
40 };
41 };
42 };
43
44 &gpio1 {
45 status = "okay";
46
47 poe_enable {
48 gpio-hog;
49 gpios = <13 0>;
50 output-high;
51 };
52 };
53
54 &spi0 {
55 status = "okay";
56
57 flash@0 {
58 compatible = "jedec,spi-nor";
59 reg = <0>;
60 spi-max-frequency = <10000000>;
61
62 partitions {
63 compatible = "fixed-partitions";
64 #address-cells = <1>;
65 #size-cells = <1>;
66
67 partition@0 {
68 label = "u-boot";
69 reg = <0x0 0x40000>;
70 read-only;
71 };
72 partition@40000 {
73 label = "u-boot-env";
74 reg = <0x40000 0x10000>;
75 read-only;
76 };
77 partition@50000 {
78 label = "u-boot-env2";
79 reg = <0x50000 0x10000>;
80 };
81 partition@60000 {
82 label = "jffs";
83 reg = <0x60000 0x100000>;
84 };
85 partition@160000 {
86 label = "jffs2";
87 reg = <0x160000 0x100000>;
88 };
89 partition@b260000 {
90 label = "firmware";
91 reg = <0x260000 0x6d0000>;
92 compatible = "openwrt,uimage", "denx,uimage";
93 openwrt,ih-magic = <0x83800000>;
94 };
95 partition@930000 {
96 label = "runtime2";
97 reg = <0x930000 0x6d0000>;
98 };
99 };
100 };
101 };
102
103 &ethernet0 {
104 mdio: mdio-bus {
105 compatible = "realtek,rtl838x-mdio";
106 regmap = <&ethernet0>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 INTERNAL_PHY(8)
111 INTERNAL_PHY(9)
112 INTERNAL_PHY(10)
113 INTERNAL_PHY(11)
114 INTERNAL_PHY(12)
115 INTERNAL_PHY(13)
116 INTERNAL_PHY(14)
117 INTERNAL_PHY(15)
118 };
119 };
120
121 &switch0 {
122 ports {
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 SWITCH_PORT(8, 1, internal)
127 SWITCH_PORT(9, 2, internal)
128 SWITCH_PORT(10, 3, internal)
129 SWITCH_PORT(11, 4, internal)
130 SWITCH_PORT(12, 5, internal)
131 SWITCH_PORT(13, 6, internal)
132 SWITCH_PORT(14, 7, internal)
133 SWITCH_PORT(15, 8, internal)
134
135 port@28 {
136 ethernet = <&ethernet0>;
137 reg = <28>;
138 phy-mode = "internal";
139
140 fixed-link {
141 speed = <1000>;
142 full-duplex;
143 };
144 };
145 };
146 };