kernel: mtdsplit_uimage: replace "allnet, uimage" parser
[openwrt/staging/jow.git] / target / linux / realtek / dts / rtl8382_allnet_all-sg8208m.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "rtl838x.dtsi"
4
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
7
8 / {
9 compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
10 model = "ALLNET ALL-SG8208M";
11
12 aliases {
13 led-boot = &led_sys;
14 led-failsafe = &led_sys;
15 led-running = &led_sys;
16 led-upgrade = &led_sys;
17 };
18
19 chosen {
20 bootargs = "console=ttyS0,115200";
21 };
22
23 memory@0 {
24 device_type = "memory";
25 reg = <0x0 0x8000000>;
26 };
27
28 keys {
29 compatible = "gpio-keys-polled";
30 poll-interval = <20>;
31
32 reset {
33 label = "reset";
34 gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_RESTART>;
36 };
37 };
38
39 leds {
40 compatible = "gpio-leds";
41
42 led_sys: sys {
43 label = "green:sys";
44 gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
45 };
46 // GPIO 25: power on/off all port leds
47 };
48 };
49
50 &gpio0 {
51 indirect-access-bus-id = <0>;
52 };
53
54 &spi0 {
55 status = "okay";
56
57 flash@0 {
58 compatible = "jedec,spi-nor";
59 reg = <0>;
60 spi-max-frequency = <10000000>;
61
62 partitions {
63 compatible = "fixed-partitions";
64 #address-cells = <1>;
65 #size-cells = <1>;
66
67 partition@0 {
68 label = "u-boot";
69 reg = <0x0 0x80000>;
70 read-only;
71 };
72
73 partition@80000 {
74 label = "u-boot-env";
75 reg = <0x80000 0x10000>;
76 read-only;
77 };
78
79 partition@90000 {
80 label = "u-boot-env2";
81 reg = <0x90000 0x10000>;
82 read-only;
83 };
84
85 partition@a0000 {
86 label = "jffs";
87 reg = <0xa0000 0x100000>;
88 };
89
90 partition@1a0000 {
91 label = "jffs2";
92 reg = <0x1a0000 0x100000>;
93 };
94
95 partition@2a0000 {
96 label = "firmware";
97 reg = <0x2a0000 0xd60000>;
98 compatible = "openwrt,uimage", "denx,uimage";
99 openwrt,ih-magic = <0x00000006>;
100 };
101 };
102 };
103 };
104
105 &ethernet0 {
106 mdio: mdio-bus {
107 compatible = "realtek,rtl838x-mdio";
108 regmap = <&ethernet0>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 INTERNAL_PHY(8)
113 INTERNAL_PHY(9)
114 INTERNAL_PHY(10)
115 INTERNAL_PHY(11)
116 INTERNAL_PHY(12)
117 INTERNAL_PHY(13)
118 INTERNAL_PHY(14)
119 INTERNAL_PHY(15)
120 };
121 };
122
123 &switch0 {
124 ports {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 SWITCH_PORT(8, 1, internal)
129 SWITCH_PORT(9, 2, internal)
130 SWITCH_PORT(10, 3, internal)
131 SWITCH_PORT(11, 4, internal)
132 SWITCH_PORT(12, 5, internal)
133 SWITCH_PORT(13, 6, internal)
134 SWITCH_PORT(14, 7, internal)
135 SWITCH_PORT(15, 8, internal)
136
137 port@28 {
138 ethernet = <&ethernet0>;
139 reg = <28>;
140 phy-mode = "internal";
141 fixed-link {
142 speed = <1000>;
143 full-duplex;
144 };
145 };
146 };
147 };