target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/dma.h

   1 #ifndef __IDT_DMA_H__
   2 #define __IDT_DMA_H__
   3
   4 /*******************************************************************************
   5  *
   6  * Copyright 2002 Integrated Device Technology, Inc.
   7  *              All rights reserved.
   8  *
   9  * DMA register definition.
  10  *
  11  *
  12  * Author : ryan.holmQVist@idt.com
  13  * Date   : 20011005
  14  * Update :
  15  *          $Log: dma.h,v $
  16  *          Revision 1.3  2002/06/06 18:34:03  astichte
  17  *          Added XXX_PhysicalAddress and XXX_VirtualAddress
  18  *
  19  *          Revision 1.2  2002/06/05 18:30:46  astichte
  20  *          Removed IDTField
  21  *
  22  *          Revision 1.1  2002/05/29 17:33:21  sysarch
  23  *          jba File moved from vcode/include/idt/acacia
  24  *
  25  *
  26  ******************************************************************************/
  27
  28 enum
  29 {
  30         DMA0_PhysicalAddress    = 0x18040000,
  31         DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
  32
  33         DMA0_VirtualAddress     = 0xb8040000,
  34         DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
  35 } ;
  36
  37 /*
  38  * DMA descriptor (in physical memory).
  39  */
  40
  41 typedef struct DMAD_s
  42 {
  43         u32                     control ;       // Control. use DMAD_*
  44         u32                     ca ;            // Current Address.
  45         u32                     devcs ;         // Device control and status.
  46         u32                     link ;          // Next descriptor in chain.
  47 } volatile *DMAD_t ;
  48
  49 enum
  50 {
  51         DMAD_size               = sizeof (struct DMAD_s),
  52         DMAD_count_b            = 0,            // in DMAD_t -> control
  53         DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
  54         DMAD_ds_b               = 20,           // in DMAD_t -> control
  55         DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
  56                 DMAD_ds_ethRcv_v        = 0,
  57                 DMAD_ds_ethXmt_v        = 0,
  58                 DMAD_ds_memToFifo_v     = 0,
  59                 DMAD_ds_fifoToMem_v     = 0,
  60                 DMAD_ds_pciToMem_v      = 0,
  61                 DMAD_ds_memToPci_v      = 0,
  62
  63         DMAD_devcmd_b           = 22,           // in DMAD_t -> control
  64         DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
  65                 DMAD_devcmd_byte_v      = 0,    //memory-to-memory
  66                 DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
  67                 DMAD_devcmd_word_v      = 2,    //memory-to-memory
  68                 DMAD_devcmd_2words_v    = 3,    //memory-to-memory
  69                 DMAD_devcmd_4words_v    = 4,    //memory-to-memory
  70                 DMAD_devcmd_6words_v    = 5,    //memory-to-memory
  71                 DMAD_devcmd_8words_v    = 6,    //memory-to-memory
  72                 DMAD_devcmd_16words_v   = 7,    //memory-to-memory
  73         DMAD_cof_b              = 25,           // chain on finished
  74         DMAD_cof_m              = 0x02000000,   //
  75         DMAD_cod_b              = 26,           // chain on done
  76         DMAD_cod_m              = 0x04000000,   //
  77         DMAD_iof_b              = 27,           // interrupt on finished
  78         DMAD_iof_m              = 0x08000000,   //
  79         DMAD_iod_b              = 28,           // interrupt on done
  80         DMAD_iod_m              = 0x10000000,   //
  81         DMAD_t_b                = 29,           // terminated
  82         DMAD_t_m                = 0x20000000,   //
  83         DMAD_d_b                = 30,           // done
  84         DMAD_d_m                = 0x40000000,   //
  85         DMAD_f_b                = 31,           // finished
  86         DMAD_f_m                = 0x80000000,   //
  87 } ;
  88
  89 /*
  90  * DMA register (within Internal Register Map).
  91  */
  92
  93 struct DMA_Chan_s
  94 {
  95         u32             dmac ;          // Control.
  96         u32             dmas ;          // Status.
  97         u32             dmasm ;         // Mask.
  98         u32             dmadptr ;       // Descriptor pointer.
  99         u32             dmandptr ;      // Next descriptor pointer.
 100 };
 101
 102 typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
 103
 104 //DMA_Channels    use DMACH_count instead
 105
 106 enum
 107 {
 108         DMAC_run_b      = 0,            //
 109         DMAC_run_m      = 0x00000001,   //
 110         DMAC_dm_b       = 1,            // done mask
 111         DMAC_dm_m       = 0x00000002,   //
 112         DMAC_mode_b     = 2,            //
 113         DMAC_mode_m     = 0x0000000c,   //
 114                 DMAC_mode_auto_v        = 0,
 115                 DMAC_mode_burst_v       = 1,
 116                 DMAC_mode_transfer_v    = 2, //usually used
 117                 DMAC_mode_reserved_v    = 3,
 118         DMAC_a_b        = 4,            //
 119         DMAC_a_m        = 0x00000010,   //
 120
 121         DMAS_f_b        = 0,            // finished (sticky)
 122         DMAS_f_m        = 0x00000001,   //
 123         DMAS_d_b        = 1,            // done (sticky)
 124         DMAS_d_m        = 0x00000002,   //
 125         DMAS_c_b        = 2,            // chain (sticky)
 126         DMAS_c_m        = 0x00000004,   //
 127         DMAS_e_b        = 3,            // error (sticky)
 128         DMAS_e_m        = 0x00000008,   //
 129         DMAS_h_b        = 4,            // halt (sticky)
 130         DMAS_h_m        = 0x00000010,   //
 131
 132         DMASM_f_b       = 0,            // finished (1=mask)
 133         DMASM_f_m       = 0x00000001,   //
 134         DMASM_d_b       = 1,            // done (1=mask)
 135         DMASM_d_m       = 0x00000002,   //
 136         DMASM_c_b       = 2,            // chain (1=mask)
 137         DMASM_c_m       = 0x00000004,   //
 138         DMASM_e_b       = 3,            // error (1=mask)
 139         DMASM_e_m       = 0x00000008,   //
 140         DMASM_h_b       = 4,            // halt (1=mask)
 141         DMASM_h_m       = 0x00000010,   //
 142 } ;
 143
 144 /*
 145  * DMA channel definitions
 146  */
 147
 148 enum
 149 {
 150         DMACH_ethRcv = 0,
 151         DMACH_ethXmt = 1,
 152         DMACH_memToFifo = 2,
 153         DMACH_fifoToMem = 3,
 154         DMACH_pciToMem = 4,
 155         DMACH_memToPci = 5,
 156
 157         DMACH_count //must be last
 158 };
 159
 160
 161 typedef struct DMAC_s
 162 {
 163         struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
 164 } volatile *DMA_t ;
 165
 166 #endif  // __IDT_DMA_H__
 167