target/linux/ramips/patches-4.3/0023-arch-mips-ralink-unify-soc-id.patch

   1 From 4ede4fbb485d0a88839df1f02371fc00755db636 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:31:41 +0100
   4 Subject: [PATCH 23/53] arch: mips: ralink: unify soc id
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/ralink/mt7620.c |   19 ++++++++-----------
   9  1 file changed, 8 insertions(+), 11 deletions(-)
  10
  11 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
  12 index da734e2..db99e9c 100644
  13 --- a/arch/mips/ralink/mt7620.c
  14 +++ b/arch/mips/ralink/mt7620.c
  15 @@ -37,9 +37,6 @@
  16  #define PMU1_CFG               0x8C
  17  #define DIG_SW_SEL             BIT(25)
  18
  19 -/* is this a MT7620 or a MT7628 */
  20 -enum mt762x_soc_type mt762x_soc;
  21 -
  22  /* clock scaling */
  23  #define CLKCFG_FDIV_MASK       0x1f00
  24  #define CLKCFG_FDIV_USB_VAL    0x0300
  25 @@ -410,7 +407,7 @@ void __init ralink_clk_init(void)
  26  #define RINT(x)                ((x) / 1000000)
  27  #define RFRAC(x)       (((x) / 1000) % 1000)
  28
  29 -       if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
  30 +       if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
  31                 if (xtal_rate == MHZ(40))
  32                         cpu_rate = MHZ(580);
  33                 else
  34 @@ -455,7 +452,7 @@ void __init ralink_clk_init(void)
  35         ralink_clk_add("10180000.wmac", xtal_rate);
  36
  37         if (IS_ENABLED(CONFIG_USB) &&
  38 -               (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
  39 +               (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7620N)) {
  40                 /*
  41                  * When the CPU goes into sleep mode, the BUS clock will be too low for
  42                  * USB to function properly
  43 @@ -543,11 +540,11 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  44
  45         if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
  46                 if (bga) {
  47 -                       mt762x_soc = MT762X_SOC_MT7620A;
  48 +                       ralink_soc = MT762X_SOC_MT7620A;
  49                         name = "MT7620A";
  50                         soc_info->compatible = "ralink,mt7620a-soc";
  51                 } else {
  52 -                       mt762x_soc = MT762X_SOC_MT7620N;
  53 +                       ralink_soc = MT762X_SOC_MT7620N;
  54                         name = "MT7620N";
  55                         soc_info->compatible = "ralink,mt7620n-soc";
  56                 }
  57 @@ -555,10 +552,10 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  58                 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
  59
  60                 if (efuse & EFUSE_MT7688) {
  61 -                       mt762x_soc = MT762X_SOC_MT7688;
  62 +                       ralink_soc = MT762X_SOC_MT7688;
  63                         name = "MT7688";
  64                 } else {
  65 -                       mt762x_soc = MT762X_SOC_MT7628AN;
  66 +                       ralink_soc = MT762X_SOC_MT7628AN;
  67                         name = "MT7628AN";
  68                 }
  69                 soc_info->compatible = "ralink,mt7628an-soc";
  70 @@ -580,7 +577,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  71                 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
  72
  73         soc_info->mem_base = MT7620_DRAM_BASE;
  74 -       if (mt762x_soc == MT762X_SOC_MT7628AN)
  75 +       if (ralink_soc == MT762X_SOC_MT7628AN)
  76                 mt7628_dram_init(soc_info);
  77         else
  78                 mt7620_dram_init(soc_info);
  79 @@ -593,7 +590,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  80         pr_info("Digital PMU set to %s control\n",
  81                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
  82
  83 -       if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
  84 +       if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688)
  85                 rt2880_pinmux_data = mt7628an_pinmux_data;
  86         else
  87                 rt2880_pinmux_data = mt7620a_pinmux_data;
  88 --
  89 1.7.10.4
  90