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kernel: update linux 3.8 to 3.8.6
[openwrt/openwrt.git] / target / linux / ramips / patches-3.8 / 0109-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch
1 From 45a8644332a85e8b099df9d467a719ded741e749 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jan 2013 09:39:02 +0100
4 Subject: [PATCH 109/121] MIPS: ralink: adds support for RT3883 SoC family
5
6 Add support code for rt3883 SOC.
7
8 The code detects the SoC and registers the clk / pinmux settings.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 ---
12 arch/mips/include/asm/mach-ralink/rt3883.h | 247 ++++++++++++++++++++++++++++
13 arch/mips/ralink/Kconfig | 5 +
14 arch/mips/ralink/Makefile | 1 +
15 arch/mips/ralink/Platform | 5 +
16 arch/mips/ralink/rt3883.c | 207 +++++++++++++++++++++++
17 5 files changed, 465 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
19 create mode 100644 arch/mips/ralink/rt3883.c
20
21 --- /dev/null
22 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
23 @@ -0,0 +1,247 @@
24 +/*
25 + * Ralink RT3662/RT3883 SoC register definitions
26 + *
27 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
28 + *
29 + * This program is free software; you can redistribute it and/or modify it
30 + * under the terms of the GNU General Public License version 2 as published
31 + * by the Free Software Foundation.
32 + */
33 +
34 +#ifndef _RT3883_REGS_H_
35 +#define _RT3883_REGS_H_
36 +
37 +#include <linux/bitops.h>
38 +
39 +#define RT3883_SDRAM_BASE 0x00000000
40 +#define RT3883_SYSC_BASE 0x10000000
41 +#define RT3883_TIMER_BASE 0x10000100
42 +#define RT3883_INTC_BASE 0x10000200
43 +#define RT3883_MEMC_BASE 0x10000300
44 +#define RT3883_UART0_BASE 0x10000500
45 +#define RT3883_PIO_BASE 0x10000600
46 +#define RT3883_FSCC_BASE 0x10000700
47 +#define RT3883_NANDC_BASE 0x10000810
48 +#define RT3883_I2C_BASE 0x10000900
49 +#define RT3883_I2S_BASE 0x10000a00
50 +#define RT3883_SPI_BASE 0x10000b00
51 +#define RT3883_UART1_BASE 0x10000c00
52 +#define RT3883_PCM_BASE 0x10002000
53 +#define RT3883_GDMA_BASE 0x10002800
54 +#define RT3883_CODEC1_BASE 0x10003000
55 +#define RT3883_CODEC2_BASE 0x10003800
56 +#define RT3883_FE_BASE 0x10100000
57 +#define RT3883_ROM_BASE 0x10118000
58 +#define RT3883_USBDEV_BASE 0x10112000
59 +#define RT3883_PCI_BASE 0x10140000
60 +#define RT3883_WLAN_BASE 0x10180000
61 +#define RT3883_USBHOST_BASE 0x101c0000
62 +#define RT3883_BOOT_BASE 0x1c000000
63 +#define RT3883_SRAM_BASE 0x1e000000
64 +#define RT3883_PCIMEM_BASE 0x20000000
65 +
66 +#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
67 +#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
68 +
69 +#define RT3883_SYSC_SIZE 0x100
70 +#define RT3883_TIMER_SIZE 0x100
71 +#define RT3883_INTC_SIZE 0x100
72 +#define RT3883_MEMC_SIZE 0x100
73 +#define RT3883_UART0_SIZE 0x100
74 +#define RT3883_UART1_SIZE 0x100
75 +#define RT3883_PIO_SIZE 0x100
76 +#define RT3883_FSCC_SIZE 0x100
77 +#define RT3883_NANDC_SIZE 0x0f0
78 +#define RT3883_I2C_SIZE 0x100
79 +#define RT3883_I2S_SIZE 0x100
80 +#define RT3883_SPI_SIZE 0x100
81 +#define RT3883_PCM_SIZE 0x800
82 +#define RT3883_GDMA_SIZE 0x800
83 +#define RT3883_CODEC1_SIZE 0x800
84 +#define RT3883_CODEC2_SIZE 0x800
85 +#define RT3883_FE_SIZE 0x10000
86 +#define RT3883_ROM_SIZE 0x4000
87 +#define RT3883_USBDEV_SIZE 0x4000
88 +#define RT3883_PCI_SIZE 0x40000
89 +#define RT3883_WLAN_SIZE 0x40000
90 +#define RT3883_USBHOST_SIZE 0x40000
91 +#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
92 +#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
93 +
94 +/* SYSC registers */
95 +#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
96 +#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
97 +#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
98 +#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
99 +#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
100 +#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
101 +#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
102 +#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
103 +#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
104 +#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
105 +#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
106 +#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
107 +#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
108 +#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
109 +#define RT3883_SYSC_REG_PMU 0x88
110 +#define RT3883_SYSC_REG_PMU1 0x8c
111 +
112 +#define RT3883_CHIP_NAME0 0x38335452
113 +#define RT3883_CHIP_NAME1 0x20203338
114 +
115 +#define RT3883_REVID_VER_ID_MASK 0x0f
116 +#define RT3883_REVID_VER_ID_SHIFT 8
117 +#define RT3883_REVID_ECO_ID_MASK 0x0f
118 +
119 +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
120 +#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
121 +#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
122 +#define RT3883_SYSCFG0_CPUCLK_250 0x0
123 +#define RT3883_SYSCFG0_CPUCLK_384 0x1
124 +#define RT3883_SYSCFG0_CPUCLK_480 0x2
125 +#define RT3883_SYSCFG0_CPUCLK_500 0x3
126 +
127 +#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
128 +#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
129 +#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
130 +#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
131 +#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
132 +
133 +#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
134 +#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
135 +#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
136 +#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
137 +
138 +#define RT3883_GPIO_MODE_I2C BIT(0)
139 +#define RT3883_GPIO_MODE_SPI BIT(1)
140 +#define RT3883_GPIO_MODE_UART0_SHIFT 2
141 +#define RT3883_GPIO_MODE_UART0_MASK 0x7
142 +#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
143 +#define RT3883_GPIO_MODE_UARTF 0x0
144 +#define RT3883_GPIO_MODE_PCM_UARTF 0x1
145 +#define RT3883_GPIO_MODE_PCM_I2S 0x2
146 +#define RT3883_GPIO_MODE_I2S_UARTF 0x3
147 +#define RT3883_GPIO_MODE_PCM_GPIO 0x4
148 +#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
149 +#define RT3883_GPIO_MODE_GPIO_I2S 0x6
150 +#define RT3883_GPIO_MODE_GPIO 0x7
151 +#define RT3883_GPIO_MODE_UART1 BIT(5)
152 +#define RT3883_GPIO_MODE_JTAG BIT(6)
153 +#define RT3883_GPIO_MODE_MDIO BIT(7)
154 +#define RT3883_GPIO_MODE_GE1 BIT(9)
155 +#define RT3883_GPIO_MODE_GE2 BIT(10)
156 +#define RT3883_GPIO_MODE_PCI_SHIFT 11
157 +#define RT3883_GPIO_MODE_PCI_MASK 0x7
158 +#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
159 +#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
160 +#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
161 +#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
162 +#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
163 +#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
164 +#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
165 +#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
166 +#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
167 +#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
168 +#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
169 +
170 +#define RT3883_GPIO_I2C_SD 1
171 +#define RT3883_GPIO_I2C_SCLK 2
172 +#define RT3883_GPIO_SPI_CS0 3
173 +#define RT3883_GPIO_SPI_CLK 4
174 +#define RT3883_GPIO_SPI_MOSI 5
175 +#define RT3883_GPIO_SPI_MISO 6
176 +#define RT3883_GPIO_7 7
177 +#define RT3883_GPIO_10 10
178 +#define RT3883_GPIO_14 14
179 +#define RT3883_GPIO_UART1_TXD 15
180 +#define RT3883_GPIO_UART1_RXD 16
181 +#define RT3883_GPIO_JTAG_TDO 17
182 +#define RT3883_GPIO_JTAG_TDI 18
183 +#define RT3883_GPIO_JTAG_TMS 19
184 +#define RT3883_GPIO_JTAG_TCLK 20
185 +#define RT3883_GPIO_JTAG_TRST_N 21
186 +#define RT3883_GPIO_MDIO_MDC 22
187 +#define RT3883_GPIO_MDIO_MDIO 23
188 +#define RT3883_GPIO_LNA_PE_A0 32
189 +#define RT3883_GPIO_LNA_PE_A1 33
190 +#define RT3883_GPIO_LNA_PE_A2 34
191 +#define RT3883_GPIO_LNA_PE_G0 35
192 +#define RT3883_GPIO_LNA_PE_G1 36
193 +#define RT3883_GPIO_LNA_PE_G2 37
194 +#define RT3883_GPIO_PCI_AD0 40
195 +#define RT3883_GPIO_PCI_AD31 71
196 +#define RT3883_GPIO_GE2_TXD0 72
197 +#define RT3883_GPIO_GE2_TXD1 73
198 +#define RT3883_GPIO_GE2_TXD2 74
199 +#define RT3883_GPIO_GE2_TXD3 75
200 +#define RT3883_GPIO_GE2_TXEN 76
201 +#define RT3883_GPIO_GE2_TXCLK 77
202 +#define RT3883_GPIO_GE2_RXD0 78
203 +#define RT3883_GPIO_GE2_RXD1 79
204 +#define RT3883_GPIO_GE2_RXD2 80
205 +#define RT3883_GPIO_GE2_RXD3 81
206 +#define RT3883_GPIO_GE2_RXDV 82
207 +#define RT3883_GPIO_GE2_RXCLK 83
208 +#define RT3883_GPIO_GE1_TXD0 84
209 +#define RT3883_GPIO_GE1_TXD1 85
210 +#define RT3883_GPIO_GE1_TXD2 86
211 +#define RT3883_GPIO_GE1_TXD3 87
212 +#define RT3883_GPIO_GE1_TXEN 88
213 +#define RT3883_GPIO_GE1_TXCLK 89
214 +#define RT3883_GPIO_GE1_RXD0 90
215 +#define RT3883_GPIO_GE1_RXD1 91
216 +#define RT3883_GPIO_GE1_RXD2 92
217 +#define RT3883_GPIO_GE1_RXD3 93
218 +#define RT3883_GPIO_GE1_RXDV 94
219 +#define RT3883_GPIO_GE1_RXCLK 95
220 +
221 +#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
222 +#define RT3883_RSTCTRL_FLASH BIT(26)
223 +#define RT3883_RSTCTRL_UDEV BIT(25)
224 +#define RT3883_RSTCTRL_PCI BIT(24)
225 +#define RT3883_RSTCTRL_PCIE BIT(23)
226 +#define RT3883_RSTCTRL_UHST BIT(22)
227 +#define RT3883_RSTCTRL_FE BIT(21)
228 +#define RT3883_RSTCTRL_WLAN BIT(20)
229 +#define RT3883_RSTCTRL_UART1 BIT(29)
230 +#define RT3883_RSTCTRL_SPI BIT(18)
231 +#define RT3883_RSTCTRL_I2S BIT(17)
232 +#define RT3883_RSTCTRL_I2C BIT(16)
233 +#define RT3883_RSTCTRL_NAND BIT(15)
234 +#define RT3883_RSTCTRL_DMA BIT(14)
235 +#define RT3883_RSTCTRL_PIO BIT(13)
236 +#define RT3883_RSTCTRL_UART BIT(12)
237 +#define RT3883_RSTCTRL_PCM BIT(11)
238 +#define RT3883_RSTCTRL_MC BIT(10)
239 +#define RT3883_RSTCTRL_INTC BIT(9)
240 +#define RT3883_RSTCTRL_TIMER BIT(8)
241 +#define RT3883_RSTCTRL_SYS BIT(0)
242 +
243 +#define RT3883_INTC_INT_SYSCTL BIT(0)
244 +#define RT3883_INTC_INT_TIMER0 BIT(1)
245 +#define RT3883_INTC_INT_TIMER1 BIT(2)
246 +#define RT3883_INTC_INT_IA BIT(3)
247 +#define RT3883_INTC_INT_PCM BIT(4)
248 +#define RT3883_INTC_INT_UART0 BIT(5)
249 +#define RT3883_INTC_INT_PIO BIT(6)
250 +#define RT3883_INTC_INT_DMA BIT(7)
251 +#define RT3883_INTC_INT_NAND BIT(8)
252 +#define RT3883_INTC_INT_PERFC BIT(9)
253 +#define RT3883_INTC_INT_I2S BIT(10)
254 +#define RT3883_INTC_INT_UART1 BIT(12)
255 +#define RT3883_INTC_INT_UHST BIT(18)
256 +#define RT3883_INTC_INT_UDEV BIT(19)
257 +
258 +/* FLASH/SRAM/Codec Controller registers */
259 +#define RT3883_FSCC_REG_FLASH_CFG0 0x00
260 +#define RT3883_FSCC_REG_FLASH_CFG1 0x04
261 +#define RT3883_FSCC_REG_CODEC_CFG0 0x40
262 +#define RT3883_FSCC_REG_CODEC_CFG1 0x44
263 +
264 +#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
265 +#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
266 +#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
267 +#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
268 +#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
269 +
270 +#endif /* _RT3883_REGS_H_ */
271 --- a/arch/mips/ralink/Kconfig
272 +++ b/arch/mips/ralink/Kconfig
273 @@ -15,6 +15,11 @@ choice
274 select USB_ARCH_HAS_OHCI
275 select USB_ARCH_HAS_EHCI
276
277 + config SOC_RT3883
278 + bool "RT3883"
279 + select USB_ARCH_HAS_OHCI
280 + select USB_ARCH_HAS_EHCI
281 +
282 endchoice
283
284 choice
285 --- a/arch/mips/ralink/Makefile
286 +++ b/arch/mips/ralink/Makefile
287 @@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
288
289 obj-$(CONFIG_SOC_RT288X) += rt288x.o
290 obj-$(CONFIG_SOC_RT305X) += rt305x.o
291 +obj-$(CONFIG_SOC_RT3883) += rt3883.o
292
293 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
294
295 --- a/arch/mips/ralink/Platform
296 +++ b/arch/mips/ralink/Platform
297 @@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X) += 0xffffffff8
298 # Ralink RT305x
299 #
300 load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
301 +
302 +#
303 +# Ralink RT3883
304 +#
305 +load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
306 --- /dev/null
307 +++ b/arch/mips/ralink/rt3883.c
308 @@ -0,0 +1,207 @@
309 +/*
310 + * This program is free software; you can redistribute it and/or modify it
311 + * under the terms of the GNU General Public License version 2 as published
312 + * by the Free Software Foundation.
313 + *
314 + * Parts of this file are based on Ralink's 2.6.21 BSP
315 + *
316 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
317 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
318 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
319 + */
320 +
321 +#include <linux/kernel.h>
322 +#include <linux/init.h>
323 +#include <linux/module.h>
324 +
325 +#include <asm/mipsregs.h>
326 +#include <asm/mach-ralink/ralink_regs.h>
327 +#include <asm/mach-ralink/rt3883.h>
328 +
329 +#include "common.h"
330 +
331 +struct ralink_pinmux_grp mode_mux[] = {
332 + {
333 + .name = "i2c",
334 + .mask = RT3883_GPIO_MODE_I2C,
335 + .gpio_first = RT3883_GPIO_I2C_SD,
336 + .gpio_last = RT3883_GPIO_I2C_SCLK,
337 + }, {
338 + .name = "spi",
339 + .mask = RT3883_GPIO_MODE_SPI,
340 + .gpio_first = RT3883_GPIO_SPI_CS0,
341 + .gpio_last = RT3883_GPIO_SPI_MISO,
342 + }, {
343 + .name = "uartlite",
344 + .mask = RT3883_GPIO_MODE_UART1,
345 + .gpio_first = RT3883_GPIO_UART1_TXD,
346 + .gpio_last = RT3883_GPIO_UART1_RXD,
347 + }, {
348 + .name = "jtag",
349 + .mask = RT3883_GPIO_MODE_JTAG,
350 + .gpio_first = RT3883_GPIO_JTAG_TDO,
351 + .gpio_last = RT3883_GPIO_JTAG_TCLK,
352 + }, {
353 + .name = "mdio",
354 + .mask = RT3883_GPIO_MODE_MDIO,
355 + .gpio_first = RT3883_GPIO_MDIO_MDC,
356 + .gpio_last = RT3883_GPIO_MDIO_MDIO,
357 + }, {
358 + .name = "ge1",
359 + .mask = RT3883_GPIO_MODE_GE1,
360 + .gpio_first = RT3883_GPIO_GE1_TXD0,
361 + .gpio_last = RT3883_GPIO_GE1_RXCLK,
362 + }, {
363 + .name = "ge2",
364 + .mask = RT3883_GPIO_MODE_GE2,
365 + .gpio_first = RT3883_GPIO_GE2_TXD0,
366 + .gpio_last = RT3883_GPIO_GE2_RXCLK,
367 + }, {
368 + .name = "pci",
369 + .mask = RT3883_GPIO_MODE_PCI,
370 + .gpio_first = RT3883_GPIO_PCI_AD0,
371 + .gpio_last = RT3883_GPIO_PCI_AD31,
372 + }, {
373 + .name = "lna a",
374 + .mask = RT3883_GPIO_MODE_LNA_A,
375 + .gpio_first = RT3883_GPIO_LNA_PE_A0,
376 + .gpio_last = RT3883_GPIO_LNA_PE_A2,
377 + }, {
378 + .name = "lna g",
379 + .mask = RT3883_GPIO_MODE_LNA_G,
380 + .gpio_first = RT3883_GPIO_LNA_PE_G0,
381 + .gpio_last = RT3883_GPIO_LNA_PE_G2,
382 + }, {0}
383 +};
384 +
385 +struct ralink_pinmux_grp uart_mux[] = {
386 + {
387 + .name = "uartf",
388 + .mask = RT3883_GPIO_MODE_UARTF,
389 + .gpio_first = RT3883_GPIO_7,
390 + .gpio_last = RT3883_GPIO_14,
391 + }, {
392 + .name = "pcm uartf",
393 + .mask = RT3883_GPIO_MODE_PCM_UARTF,
394 + .gpio_first = RT3883_GPIO_7,
395 + .gpio_last = RT3883_GPIO_14,
396 + }, {
397 + .name = "pcm i2s",
398 + .mask = RT3883_GPIO_MODE_PCM_I2S,
399 + .gpio_first = RT3883_GPIO_7,
400 + .gpio_last = RT3883_GPIO_14,
401 + }, {
402 + .name = "i2s uartf",
403 + .mask = RT3883_GPIO_MODE_I2S_UARTF,
404 + .gpio_first = RT3883_GPIO_7,
405 + .gpio_last = RT3883_GPIO_14,
406 + }, {
407 + .name = "pcm gpio",
408 + .mask = RT3883_GPIO_MODE_PCM_GPIO,
409 + .gpio_first = RT3883_GPIO_10,
410 + .gpio_last = RT3883_GPIO_14,
411 + }, {
412 + .name = "gpio uartf",
413 + .mask = RT3883_GPIO_MODE_GPIO_UARTF,
414 + .gpio_first = RT3883_GPIO_7,
415 + .gpio_last = RT3883_GPIO_14,
416 + }, {
417 + .name = "gpio i2s",
418 + .mask = RT3883_GPIO_MODE_GPIO_I2S,
419 + .gpio_first = RT3883_GPIO_7,
420 + .gpio_last = RT3883_GPIO_14,
421 + }, {0}
422 +};
423 +
424 +static void rt3883_wdt_reset(void)
425 +{
426 + u32 t;
427 +
428 + /* enable WDT reset output on GPIO 2 */
429 + t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
430 + t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
431 + rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
432 +}
433 +
434 +struct ralink_pinmux rt_pinmux = {
435 + .mode = mode_mux,
436 + .uart = uart_mux,
437 + .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
438 + .uart_mask = RT3883_GPIO_MODE_GPIO,
439 + .wdt_reset = rt3883_wdt_reset,
440 +};
441 +
442 +void __init ralink_clk_init(void)
443 +{
444 + unsigned long cpu_rate, sys_rate;
445 + u32 syscfg0;
446 + u32 clksel;
447 + u32 ddr2;
448 +
449 + syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
450 + clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
451 + RT3883_SYSCFG0_CPUCLK_MASK);
452 + ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
453 +
454 + switch (clksel) {
455 + case RT3883_SYSCFG0_CPUCLK_250:
456 + cpu_rate = 250000000;
457 + sys_rate = (ddr2) ? 125000000 : 83000000;
458 + break;
459 + case RT3883_SYSCFG0_CPUCLK_384:
460 + cpu_rate = 384000000;
461 + sys_rate = (ddr2) ? 128000000 : 96000000;
462 + break;
463 + case RT3883_SYSCFG0_CPUCLK_480:
464 + cpu_rate = 480000000;
465 + sys_rate = (ddr2) ? 160000000 : 120000000;
466 + break;
467 + case RT3883_SYSCFG0_CPUCLK_500:
468 + cpu_rate = 500000000;
469 + sys_rate = (ddr2) ? 166000000 : 125000000;
470 + break;
471 + }
472 +
473 + ralink_clk_add("cpu", cpu_rate);
474 + ralink_clk_add("10000100.timer", sys_rate);
475 + ralink_clk_add("10000120.watchdog", sys_rate);
476 + ralink_clk_add("10000500.uart", 40000000);
477 + ralink_clk_add("10000b00.spi", sys_rate);
478 + ralink_clk_add("10000c00.uartlite", 40000000);
479 + ralink_clk_add("10100000.ethernet", sys_rate);
480 +}
481 +
482 +void __init ralink_of_remap(void)
483 +{
484 + rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
485 + rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
486 +
487 + if (!rt_sysc_membase || !rt_memc_membase)
488 + panic("Failed to remap core resources");
489 +}
490 +
491 +void prom_soc_init(struct ralink_soc_info *soc_info)
492 +{
493 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
494 + const char *name;
495 + u32 n0;
496 + u32 n1;
497 + u32 id;
498 +
499 + n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
500 + n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
501 + id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
502 +
503 + if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
504 + soc_info->compatible = "ralink,rt3883-soc";
505 + name = "RT3883";
506 + } else {
507 + panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
508 + }
509 +
510 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
511 + "Ralink %s ver:%u eco:%u",
512 + name,
513 + (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
514 + (id & RT3883_REVID_ECO_ID_MASK));
515 +}
OpenWrt Source Repository