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kernel: update linux 3.8 to 3.8.6
[openwrt/openwrt.git] / target / linux / ramips / patches-3.8 / 0008-MIPS-ralink-adds-support-for-RT305x-SoC-family.patch
1 From 2809b31770d7fd934a748692e1922a5e613f06e5 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 20 Jan 2013 22:03:46 +0100
4 Subject: [PATCH 08/14] MIPS: ralink: adds support for RT305x SoC family
5
6 Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC.
7
8 The code detects the SoC and registers the clk / pinmux settings.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
12 Patchwork: http://patchwork.linux-mips.org/patch/4896/
13 ---
14 arch/mips/include/asm/mach-ralink/rt305x.h | 139 ++++++++++++++++
15 arch/mips/ralink/rt305x.c | 242 ++++++++++++++++++++++++++++
16 2 files changed, 381 insertions(+)
17 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h
18 create mode 100644 arch/mips/ralink/rt305x.c
19
20 --- /dev/null
21 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
22 @@ -0,0 +1,139 @@
23 +/*
24 + * This program is free software; you can redistribute it and/or modify it
25 + * under the terms of the GNU General Public License version 2 as published
26 + * by the Free Software Foundation.
27 + *
28 + * Parts of this file are based on Ralink's 2.6.21 BSP
29 + *
30 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
31 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
32 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
33 + */
34 +
35 +#ifndef _RT305X_REGS_H_
36 +#define _RT305X_REGS_H_
37 +
38 +enum rt305x_soc_type {
39 + RT305X_SOC_UNKNOWN = 0,
40 + RT305X_SOC_RT3050,
41 + RT305X_SOC_RT3052,
42 + RT305X_SOC_RT3350,
43 + RT305X_SOC_RT3352,
44 + RT305X_SOC_RT5350,
45 +};
46 +
47 +extern enum rt305x_soc_type rt305x_soc;
48 +
49 +static inline int soc_is_rt3050(void)
50 +{
51 + return rt305x_soc == RT305X_SOC_RT3050;
52 +}
53 +
54 +static inline int soc_is_rt3052(void)
55 +{
56 + return rt305x_soc == RT305X_SOC_RT3052;
57 +}
58 +
59 +static inline int soc_is_rt305x(void)
60 +{
61 + return soc_is_rt3050() || soc_is_rt3052();
62 +}
63 +
64 +static inline int soc_is_rt3350(void)
65 +{
66 + return rt305x_soc == RT305X_SOC_RT3350;
67 +}
68 +
69 +static inline int soc_is_rt3352(void)
70 +{
71 + return rt305x_soc == RT305X_SOC_RT3352;
72 +}
73 +
74 +static inline int soc_is_rt5350(void)
75 +{
76 + return rt305x_soc == RT305X_SOC_RT5350;
77 +}
78 +
79 +#define RT305X_SYSC_BASE 0x10000000
80 +
81 +#define SYSC_REG_CHIP_NAME0 0x00
82 +#define SYSC_REG_CHIP_NAME1 0x04
83 +#define SYSC_REG_CHIP_ID 0x0c
84 +#define SYSC_REG_SYSTEM_CONFIG 0x10
85 +
86 +#define RT3052_CHIP_NAME0 0x30335452
87 +#define RT3052_CHIP_NAME1 0x20203235
88 +
89 +#define RT3350_CHIP_NAME0 0x33335452
90 +#define RT3350_CHIP_NAME1 0x20203035
91 +
92 +#define RT3352_CHIP_NAME0 0x33335452
93 +#define RT3352_CHIP_NAME1 0x20203235
94 +
95 +#define RT5350_CHIP_NAME0 0x33355452
96 +#define RT5350_CHIP_NAME1 0x20203035
97 +
98 +#define CHIP_ID_ID_MASK 0xff
99 +#define CHIP_ID_ID_SHIFT 8
100 +#define CHIP_ID_REV_MASK 0xff
101 +
102 +#define RT305X_SYSCFG_CPUCLK_SHIFT 18
103 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1
104 +#define RT305X_SYSCFG_CPUCLK_LOW 0x0
105 +#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
106 +
107 +#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
108 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1
109 +#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
110 +
111 +#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
112 +#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
113 +#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
114 +#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
115 +
116 +#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
117 +#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
118 +#define RT5350_SYSCFG0_CPUCLK_360 0x0
119 +#define RT5350_SYSCFG0_CPUCLK_320 0x2
120 +#define RT5350_SYSCFG0_CPUCLK_300 0x3
121 +
122 +/* multi function gpio pins */
123 +#define RT305X_GPIO_I2C_SD 1
124 +#define RT305X_GPIO_I2C_SCLK 2
125 +#define RT305X_GPIO_SPI_EN 3
126 +#define RT305X_GPIO_SPI_CLK 4
127 +/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
128 +#define RT305X_GPIO_7 7
129 +#define RT305X_GPIO_10 10
130 +#define RT305X_GPIO_14 14
131 +#define RT305X_GPIO_UART1_TXD 15
132 +#define RT305X_GPIO_UART1_RXD 16
133 +#define RT305X_GPIO_JTAG_TDO 17
134 +#define RT305X_GPIO_JTAG_TDI 18
135 +#define RT305X_GPIO_MDIO_MDC 22
136 +#define RT305X_GPIO_MDIO_MDIO 23
137 +#define RT305X_GPIO_SDRAM_MD16 24
138 +#define RT305X_GPIO_SDRAM_MD31 39
139 +#define RT305X_GPIO_GE0_TXD0 40
140 +#define RT305X_GPIO_GE0_RXCLK 51
141 +
142 +#define RT305X_GPIO_MODE_I2C BIT(0)
143 +#define RT305X_GPIO_MODE_SPI BIT(1)
144 +#define RT305X_GPIO_MODE_UART0_SHIFT 2
145 +#define RT305X_GPIO_MODE_UART0_MASK 0x7
146 +#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
147 +#define RT305X_GPIO_MODE_UARTF 0x0
148 +#define RT305X_GPIO_MODE_PCM_UARTF 0x1
149 +#define RT305X_GPIO_MODE_PCM_I2S 0x2
150 +#define RT305X_GPIO_MODE_I2S_UARTF 0x3
151 +#define RT305X_GPIO_MODE_PCM_GPIO 0x4
152 +#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
153 +#define RT305X_GPIO_MODE_GPIO_I2S 0x6
154 +#define RT305X_GPIO_MODE_GPIO 0x7
155 +#define RT305X_GPIO_MODE_UART1 BIT(5)
156 +#define RT305X_GPIO_MODE_JTAG BIT(6)
157 +#define RT305X_GPIO_MODE_MDIO BIT(7)
158 +#define RT305X_GPIO_MODE_SDRAM BIT(8)
159 +#define RT305X_GPIO_MODE_RGMII BIT(9)
160 +
161 +#endif
162 --- /dev/null
163 +++ b/arch/mips/ralink/rt305x.c
164 @@ -0,0 +1,242 @@
165 +/*
166 + * This program is free software; you can redistribute it and/or modify it
167 + * under the terms of the GNU General Public License version 2 as published
168 + * by the Free Software Foundation.
169 + *
170 + * Parts of this file are based on Ralink's 2.6.21 BSP
171 + *
172 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
173 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
174 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
175 + */
176 +
177 +#include <linux/kernel.h>
178 +#include <linux/init.h>
179 +#include <linux/module.h>
180 +
181 +#include <asm/mipsregs.h>
182 +#include <asm/mach-ralink/ralink_regs.h>
183 +#include <asm/mach-ralink/rt305x.h>
184 +
185 +#include "common.h"
186 +
187 +enum rt305x_soc_type rt305x_soc;
188 +
189 +struct ralink_pinmux_grp mode_mux[] = {
190 + {
191 + .name = "i2c",
192 + .mask = RT305X_GPIO_MODE_I2C,
193 + .gpio_first = RT305X_GPIO_I2C_SD,
194 + .gpio_last = RT305X_GPIO_I2C_SCLK,
195 + }, {
196 + .name = "spi",
197 + .mask = RT305X_GPIO_MODE_SPI,
198 + .gpio_first = RT305X_GPIO_SPI_EN,
199 + .gpio_last = RT305X_GPIO_SPI_CLK,
200 + }, {
201 + .name = "uartlite",
202 + .mask = RT305X_GPIO_MODE_UART1,
203 + .gpio_first = RT305X_GPIO_UART1_TXD,
204 + .gpio_last = RT305X_GPIO_UART1_RXD,
205 + }, {
206 + .name = "jtag",
207 + .mask = RT305X_GPIO_MODE_JTAG,
208 + .gpio_first = RT305X_GPIO_JTAG_TDO,
209 + .gpio_last = RT305X_GPIO_JTAG_TDI,
210 + }, {
211 + .name = "mdio",
212 + .mask = RT305X_GPIO_MODE_MDIO,
213 + .gpio_first = RT305X_GPIO_MDIO_MDC,
214 + .gpio_last = RT305X_GPIO_MDIO_MDIO,
215 + }, {
216 + .name = "sdram",
217 + .mask = RT305X_GPIO_MODE_SDRAM,
218 + .gpio_first = RT305X_GPIO_SDRAM_MD16,
219 + .gpio_last = RT305X_GPIO_SDRAM_MD31,
220 + }, {
221 + .name = "rgmii",
222 + .mask = RT305X_GPIO_MODE_RGMII,
223 + .gpio_first = RT305X_GPIO_GE0_TXD0,
224 + .gpio_last = RT305X_GPIO_GE0_RXCLK,
225 + }, {0}
226 +};
227 +
228 +struct ralink_pinmux_grp uart_mux[] = {
229 + {
230 + .name = "uartf",
231 + .mask = RT305X_GPIO_MODE_UARTF,
232 + .gpio_first = RT305X_GPIO_7,
233 + .gpio_last = RT305X_GPIO_14,
234 + }, {
235 + .name = "pcm uartf",
236 + .mask = RT305X_GPIO_MODE_PCM_UARTF,
237 + .gpio_first = RT305X_GPIO_7,
238 + .gpio_last = RT305X_GPIO_14,
239 + }, {
240 + .name = "pcm i2s",
241 + .mask = RT305X_GPIO_MODE_PCM_I2S,
242 + .gpio_first = RT305X_GPIO_7,
243 + .gpio_last = RT305X_GPIO_14,
244 + }, {
245 + .name = "i2s uartf",
246 + .mask = RT305X_GPIO_MODE_I2S_UARTF,
247 + .gpio_first = RT305X_GPIO_7,
248 + .gpio_last = RT305X_GPIO_14,
249 + }, {
250 + .name = "pcm gpio",
251 + .mask = RT305X_GPIO_MODE_PCM_GPIO,
252 + .gpio_first = RT305X_GPIO_10,
253 + .gpio_last = RT305X_GPIO_14,
254 + }, {
255 + .name = "gpio uartf",
256 + .mask = RT305X_GPIO_MODE_GPIO_UARTF,
257 + .gpio_first = RT305X_GPIO_7,
258 + .gpio_last = RT305X_GPIO_14,
259 + }, {
260 + .name = "gpio i2s",
261 + .mask = RT305X_GPIO_MODE_GPIO_I2S,
262 + .gpio_first = RT305X_GPIO_7,
263 + .gpio_last = RT305X_GPIO_14,
264 + }, {
265 + .name = "gpio",
266 + .mask = RT305X_GPIO_MODE_GPIO,
267 + }, {0}
268 +};
269 +
270 +void rt305x_wdt_reset(void)
271 +{
272 + u32 t;
273 +
274 + /* enable WDT reset output on pin SRAM_CS_N */
275 + t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
276 + t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
277 + RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
278 + rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
279 +}
280 +
281 +struct ralink_pinmux gpio_pinmux = {
282 + .mode = mode_mux,
283 + .uart = uart_mux,
284 + .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
285 + .wdt_reset = rt305x_wdt_reset,
286 +};
287 +
288 +void __init ralink_clk_init(void)
289 +{
290 + unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
291 + u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
292 +
293 + if (soc_is_rt305x() || soc_is_rt3350()) {
294 + t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
295 + RT305X_SYSCFG_CPUCLK_MASK;
296 + switch (t) {
297 + case RT305X_SYSCFG_CPUCLK_LOW:
298 + cpu_rate = 320000000;
299 + break;
300 + case RT305X_SYSCFG_CPUCLK_HIGH:
301 + cpu_rate = 384000000;
302 + break;
303 + }
304 + sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
305 + } else if (soc_is_rt3352()) {
306 + t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
307 + RT3352_SYSCFG0_CPUCLK_MASK;
308 + switch (t) {
309 + case RT3352_SYSCFG0_CPUCLK_LOW:
310 + cpu_rate = 384000000;
311 + break;
312 + case RT3352_SYSCFG0_CPUCLK_HIGH:
313 + cpu_rate = 400000000;
314 + break;
315 + }
316 + sys_rate = wdt_rate = cpu_rate / 3;
317 + uart_rate = 40000000;
318 + } else if (soc_is_rt5350()) {
319 + t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
320 + RT5350_SYSCFG0_CPUCLK_MASK;
321 + switch (t) {
322 + case RT5350_SYSCFG0_CPUCLK_360:
323 + cpu_rate = 360000000;
324 + sys_rate = cpu_rate / 3;
325 + break;
326 + case RT5350_SYSCFG0_CPUCLK_320:
327 + cpu_rate = 320000000;
328 + sys_rate = cpu_rate / 4;
329 + break;
330 + case RT5350_SYSCFG0_CPUCLK_300:
331 + cpu_rate = 300000000;
332 + sys_rate = cpu_rate / 3;
333 + break;
334 + default:
335 + BUG();
336 + }
337 + uart_rate = 40000000;
338 + wdt_rate = sys_rate;
339 + } else {
340 + BUG();
341 + }
342 +
343 + ralink_clk_add("cpu", cpu_rate);
344 + ralink_clk_add("10000b00.spi", sys_rate);
345 + ralink_clk_add("10000100.timer", wdt_rate);
346 + ralink_clk_add("10000500.uart", uart_rate);
347 + ralink_clk_add("10000c00.uartlite", uart_rate);
348 +}
349 +
350 +void __init ralink_of_remap(void)
351 +{
352 + rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
353 + rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
354 +
355 + if (!rt_sysc_membase || !rt_memc_membase)
356 + panic("Failed to remap core resources");
357 +}
358 +
359 +void prom_soc_init(struct ralink_soc_info *soc_info)
360 +{
361 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
362 + unsigned char *name;
363 + u32 n0;
364 + u32 n1;
365 + u32 id;
366 +
367 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
368 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
369 +
370 + if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
371 + unsigned long icache_sets;
372 +
373 + icache_sets = (read_c0_config1() >> 22) & 7;
374 + if (icache_sets == 1) {
375 + rt305x_soc = RT305X_SOC_RT3050;
376 + name = "RT3050";
377 + soc_info->compatible = "ralink,rt3050-soc";
378 + } else {
379 + rt305x_soc = RT305X_SOC_RT3052;
380 + name = "RT3052";
381 + soc_info->compatible = "ralink,rt3052-soc";
382 + }
383 + } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
384 + rt305x_soc = RT305X_SOC_RT3350;
385 + name = "RT3350";
386 + soc_info->compatible = "ralink,rt3350-soc";
387 + } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
388 + rt305x_soc = RT305X_SOC_RT3352;
389 + name = "RT3352";
390 + soc_info->compatible = "ralink,rt3352-soc";
391 + } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
392 + rt305x_soc = RT305X_SOC_RT5350;
393 + name = "RT5350";
394 + soc_info->compatible = "ralink,rt5350-soc";
395 + } else {
396 + panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
397 + }
398 +
399 + id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
400 +
401 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
402 + "Ralink %s id:%u rev:%u",
403 + name,
404 + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
405 + (id & CHIP_ID_REV_MASK));
406 +}
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