target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   based on Ralink SDK3.3
  16  *   Copyright (C) 2009 John Crispin <blogic@openwrt.org>
  17  */
  18
  19 #ifndef RAMIPS_ETH_H
  20 #define RAMIPS_ETH_H
  21
  22 #include <linux/mii.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #define NUM_RX_DESC     256
  28 #define NUM_TX_DESC     256
  29
  30 #define RAMIPS_DELAY_EN_INT             0x80
  31 #define RAMIPS_DELAY_MAX_INT            0x04
  32 #define RAMIPS_DELAY_MAX_TOUT           0x04
  33 #define RAMIPS_DELAY_CHAN               (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT)
  34 #define RAMIPS_DELAY_INIT               ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN)
  35 #define RAMIPS_PSE_FQFC_CFG_INIT        0x80504000
  36
  37 /* interrupt bits */
  38 #define RAMIPS_CNT_PPE_AF               BIT(31)
  39 #define RAMIPS_CNT_GDM_AF               BIT(29)
  40 #define RAMIPS_PSE_P2_FC                BIT(26)
  41 #define RAMIPS_PSE_BUF_DROP             BIT(24)
  42 #define RAMIPS_GDM_OTHER_DROP           BIT(23)
  43 #define RAMIPS_PSE_P1_FC                BIT(22)
  44 #define RAMIPS_PSE_P0_FC                BIT(21)
  45 #define RAMIPS_PSE_FQ_EMPTY             BIT(20)
  46 #define RAMIPS_GE1_STA_CHG              BIT(18)
  47 #define RAMIPS_TX_COHERENT              BIT(17)
  48 #define RAMIPS_RX_COHERENT              BIT(16)
  49 #define RAMIPS_TX_DONE_INT3             BIT(11)
  50 #define RAMIPS_TX_DONE_INT2             BIT(10)
  51 #define RAMIPS_TX_DONE_INT1             BIT(9)
  52 #define RAMIPS_TX_DONE_INT0             BIT(8)
  53 #define RAMIPS_RX_DONE_INT0             BIT(2)
  54 #define RAMIPS_TX_DLY_INT               BIT(1)
  55 #define RAMIPS_RX_DLY_INT               BIT(0)
  56
  57 #define RT5350_RX_DLY_INT               BIT(30)
  58 #define RT5350_TX_DLY_INT               BIT(28)
  59
  60 /* registers */
  61 #define RAMIPS_FE_OFFSET                0x0000
  62 #define RAMIPS_GDMA_OFFSET              0x0020
  63 #define RAMIPS_PSE_OFFSET               0x0040
  64 #define RAMIPS_GDMA2_OFFSET             0x0060
  65 #define RAMIPS_CDMA_OFFSET              0x0080
  66 #define RAMIPS_PDMA_OFFSET              0x0100
  67 #define RAMIPS_PPE_OFFSET               0x0200
  68 #define RAMIPS_CMTABLE_OFFSET           0x0400
  69 #define RAMIPS_POLICYTABLE_OFFSET       0x1000
  70
  71 #define RT5350_PDMA_OFFSET              0x0800
  72 #define RT5350_SDM_OFFSET               0x0c00
  73
  74 #define RAMIPS_MDIO_ACCESS              (RAMIPS_FE_OFFSET + 0x00)
  75 #define RAMIPS_MDIO_CFG                 (RAMIPS_FE_OFFSET + 0x04)
  76 #define RAMIPS_FE_GLO_CFG               (RAMIPS_FE_OFFSET + 0x08)
  77 #define RAMIPS_FE_RST_GL                (RAMIPS_FE_OFFSET + 0x0C)
  78 #define RAMIPS_FE_INT_STATUS            (RAMIPS_FE_OFFSET + 0x10)
  79 #define RAMIPS_FE_INT_ENABLE            (RAMIPS_FE_OFFSET + 0x14)
  80 #define RAMIPS_MDIO_CFG2                (RAMIPS_FE_OFFSET + 0x18)
  81 #define RAMIPS_FOC_TS_T                 (RAMIPS_FE_OFFSET + 0x1C)
  82
  83 #define RAMIPS_GDMA1_FWD_CFG            (RAMIPS_GDMA_OFFSET + 0x00)
  84 #define RAMIPS_GDMA1_SCH_CFG            (RAMIPS_GDMA_OFFSET + 0x04)
  85 #define RAMIPS_GDMA1_SHPR_CFG           (RAMIPS_GDMA_OFFSET + 0x08)
  86 #define RAMIPS_GDMA1_MAC_ADRL           (RAMIPS_GDMA_OFFSET + 0x0C)
  87 #define RAMIPS_GDMA1_MAC_ADRH           (RAMIPS_GDMA_OFFSET + 0x10)
  88
  89 #define RAMIPS_GDMA2_FWD_CFG            (RAMIPS_GDMA2_OFFSET + 0x00)
  90 #define RAMIPS_GDMA2_SCH_CFG            (RAMIPS_GDMA2_OFFSET + 0x04)
  91 #define RAMIPS_GDMA2_SHPR_CFG           (RAMIPS_GDMA2_OFFSET + 0x08)
  92 #define RAMIPS_GDMA2_MAC_ADRL           (RAMIPS_GDMA2_OFFSET + 0x0C)
  93 #define RAMIPS_GDMA2_MAC_ADRH           (RAMIPS_GDMA2_OFFSET + 0x10)
  94
  95 #define RAMIPS_PSE_FQ_CFG               (RAMIPS_PSE_OFFSET + 0x00)
  96 #define RAMIPS_CDMA_FC_CFG              (RAMIPS_PSE_OFFSET + 0x04)
  97 #define RAMIPS_GDMA1_FC_CFG             (RAMIPS_PSE_OFFSET + 0x08)
  98 #define RAMIPS_GDMA2_FC_CFG             (RAMIPS_PSE_OFFSET + 0x0C)
  99
 100 #define RAMIPS_CDMA_CSG_CFG             (RAMIPS_CDMA_OFFSET + 0x00)
 101 #define RAMIPS_CDMA_SCH_CFG             (RAMIPS_CDMA_OFFSET + 0x04)
 102
 103 #define RT5350_TX_BASE_PTR0             (RT5350_PDMA_OFFSET + 0x00)
 104 #define RT5350_TX_MAX_CNT0              (RT5350_PDMA_OFFSET + 0x04)
 105 #define RT5350_TX_CTX_IDX0              (RT5350_PDMA_OFFSET + 0x08)
 106 #define RT5350_TX_DTX_IDX0              (RT5350_PDMA_OFFSET + 0x0C)
 107 #define RT5350_TX_BASE_PTR1             (RT5350_PDMA_OFFSET + 0x10)
 108 #define RT5350_TX_MAX_CNT1              (RT5350_PDMA_OFFSET + 0x14)
 109 #define RT5350_TX_CTX_IDX1              (RT5350_PDMA_OFFSET + 0x18)
 110 #define RT5350_TX_DTX_IDX1              (RT5350_PDMA_OFFSET + 0x1C)
 111 #define RT5350_TX_BASE_PTR2             (RT5350_PDMA_OFFSET + 0x20)
 112 #define RT5350_TX_MAX_CNT2              (RT5350_PDMA_OFFSET + 0x24)
 113 #define RT5350_TX_CTX_IDX2              (RT5350_PDMA_OFFSET + 0x28)
 114 #define RT5350_TX_DTX_IDX2              (RT5350_PDMA_OFFSET + 0x2C)
 115 #define RT5350_TX_BASE_PTR3             (RT5350_PDMA_OFFSET + 0x30)
 116 #define RT5350_TX_MAX_CNT3              (RT5350_PDMA_OFFSET + 0x34)
 117 #define RT5350_TX_CTX_IDX3              (RT5350_PDMA_OFFSET + 0x38)
 118 #define RT5350_TX_DTX_IDX3              (RT5350_PDMA_OFFSET + 0x3C)
 119 #define RT5350_RX_BASE_PTR0             (RT5350_PDMA_OFFSET + 0x100)
 120 #define RT5350_RX_MAX_CNT0              (RT5350_PDMA_OFFSET + 0x104)
 121 #define RT5350_RX_CALC_IDX0             (RT5350_PDMA_OFFSET + 0x108)
 122 #define RT5350_RX_DRX_IDX0              (RT5350_PDMA_OFFSET + 0x10C)
 123 #define RT5350_RX_BASE_PTR1             (RT5350_PDMA_OFFSET + 0x110)
 124 #define RT5350_RX_MAX_CNT1              (RT5350_PDMA_OFFSET + 0x114)
 125 #define RT5350_RX_CALC_IDX1             (RT5350_PDMA_OFFSET + 0x118)
 126 #define RT5350_RX_DRX_IDX1              (RT5350_PDMA_OFFSET + 0x11C)
 127 #define RT5350_PDMA_GLO_CFG             (RT5350_PDMA_OFFSET + 0x204)
 128 #define RT5350_PDMA_RST_CFG             (RT5350_PDMA_OFFSET + 0x208)
 129 #define RT5350_DLY_INT_CFG              (RT5350_PDMA_OFFSET + 0x20c)
 130 #define RT5350_FE_INT_STATUS            (RT5350_PDMA_OFFSET + 0x220)
 131 #define RT5350_FE_INT_ENABLE            (RT5350_PDMA_OFFSET + 0x228)
 132 #define RT5350_PDMA_SCH_CFG             (RT5350_PDMA_OFFSET + 0x280)
 133
 134
 135 #define RAMIPS_PDMA_GLO_CFG             (RAMIPS_PDMA_OFFSET + 0x00)
 136 #define RAMIPS_PDMA_RST_CFG             (RAMIPS_PDMA_OFFSET + 0x04)
 137 #define RAMIPS_PDMA_SCH_CFG             (RAMIPS_PDMA_OFFSET + 0x08)
 138 #define RAMIPS_DLY_INT_CFG              (RAMIPS_PDMA_OFFSET + 0x0C)
 139 #define RAMIPS_TX_BASE_PTR0             (RAMIPS_PDMA_OFFSET + 0x10)
 140 #define RAMIPS_TX_MAX_CNT0              (RAMIPS_PDMA_OFFSET + 0x14)
 141 #define RAMIPS_TX_CTX_IDX0              (RAMIPS_PDMA_OFFSET + 0x18)
 142 #define RAMIPS_TX_DTX_IDX0              (RAMIPS_PDMA_OFFSET + 0x1C)
 143 #define RAMIPS_TX_BASE_PTR1             (RAMIPS_PDMA_OFFSET + 0x20)
 144 #define RAMIPS_TX_MAX_CNT1              (RAMIPS_PDMA_OFFSET + 0x24)
 145 #define RAMIPS_TX_CTX_IDX1              (RAMIPS_PDMA_OFFSET + 0x28)
 146 #define RAMIPS_TX_DTX_IDX1              (RAMIPS_PDMA_OFFSET + 0x2C)
 147 #define RAMIPS_RX_BASE_PTR0             (RAMIPS_PDMA_OFFSET + 0x30)
 148 #define RAMIPS_RX_MAX_CNT0              (RAMIPS_PDMA_OFFSET + 0x34)
 149 #define RAMIPS_RX_CALC_IDX0             (RAMIPS_PDMA_OFFSET + 0x38)
 150 #define RAMIPS_RX_DRX_IDX0              (RAMIPS_PDMA_OFFSET + 0x3C)
 151 #define RAMIPS_TX_BASE_PTR2             (RAMIPS_PDMA_OFFSET + 0x40)
 152 #define RAMIPS_TX_MAX_CNT2              (RAMIPS_PDMA_OFFSET + 0x44)
 153 #define RAMIPS_TX_CTX_IDX2              (RAMIPS_PDMA_OFFSET + 0x48)
 154 #define RAMIPS_TX_DTX_IDX2              (RAMIPS_PDMA_OFFSET + 0x4C)
 155 #define RAMIPS_TX_BASE_PTR3             (RAMIPS_PDMA_OFFSET + 0x50)
 156 #define RAMIPS_TX_MAX_CNT3              (RAMIPS_PDMA_OFFSET + 0x54)
 157 #define RAMIPS_TX_CTX_IDX3              (RAMIPS_PDMA_OFFSET + 0x58)
 158 #define RAMIPS_TX_DTX_IDX3              (RAMIPS_PDMA_OFFSET + 0x5C)
 159 #define RAMIPS_RX_BASE_PTR1             (RAMIPS_PDMA_OFFSET + 0x60)
 160 #define RAMIPS_RX_MAX_CNT1              (RAMIPS_PDMA_OFFSET + 0x64)
 161 #define RAMIPS_RX_CALC_IDX1             (RAMIPS_PDMA_OFFSET + 0x68)
 162 #define RAMIPS_RX_DRX_IDX1              (RAMIPS_PDMA_OFFSET + 0x6C)
 163
 164 #define RT5350_SDM_CFG                  (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
 165 #define RT5350_SDM_RRING                (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
 166 #define RT5350_SDM_TRING                (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
 167 #define RT5350_SDM_MAC_ADRL             (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
 168 #define RT5350_SDM_MAC_ADRH             (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
 169 #define RT5350_SDM_TPCNT                (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
 170 #define RT5350_SDM_TBCNT                (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
 171 #define RT5350_SDM_RPCNT                (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
 172 #define RT5350_SDM_RBCNT                (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
 173 #define RT5350_SDM_CS_ERR               (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
 174
 175 #define RT5350_SDM_ICS_EN               BIT(16)
 176 #define RT5350_SDM_TCS_EN               BIT(17)
 177 #define RT5350_SDM_UCS_EN               BIT(18)
 178
 179
 180 /* MDIO_CFG register bits */
 181 #define RAMIPS_MDIO_CFG_AUTO_POLL_EN    BIT(29)
 182 #define RAMIPS_MDIO_CFG_GP1_BP_EN       BIT(16)
 183 #define RAMIPS_MDIO_CFG_GP1_FRC_EN      BIT(15)
 184 #define RAMIPS_MDIO_CFG_GP1_SPEED_10    (0 << 13)
 185 #define RAMIPS_MDIO_CFG_GP1_SPEED_100   (1 << 13)
 186 #define RAMIPS_MDIO_CFG_GP1_SPEED_1000  (2 << 13)
 187 #define RAMIPS_MDIO_CFG_GP1_DUPLEX      BIT(12)
 188 #define RAMIPS_MDIO_CFG_GP1_FC_TX       BIT(11)
 189 #define RAMIPS_MDIO_CFG_GP1_FC_RX       BIT(10)
 190 #define RAMIPS_MDIO_CFG_GP1_LNK_DWN     BIT(9)
 191 #define RAMIPS_MDIO_CFG_GP1_AN_FAIL     BIT(8)
 192 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1   (0 << 6)
 193 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2   (1 << 6)
 194 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4   (2 << 6)
 195 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8   (3 << 6)
 196 #define RAMIPS_MDIO_CFG_TURBO_MII_FREQ  BIT(5)
 197 #define RAMIPS_MDIO_CFG_TURBO_MII_MODE  BIT(4)
 198 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0   (0 << 2)
 199 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
 200 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
 201 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
 202 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0   0
 203 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
 204 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
 205 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
 206
 207 /* uni-cast port */
 208 #define RAMIPS_GDM1_ICS_EN              BIT(22)
 209 #define RAMIPS_GDM1_TCS_EN              BIT(21)
 210 #define RAMIPS_GDM1_UCS_EN              BIT(20)
 211 #define RAMIPS_GDM1_JMB_EN              BIT(19)
 212 #define RAMIPS_GDM1_STRPCRC             BIT(16)
 213 #define RAMIPS_GDM1_UFRC_P_CPU          (0 << 12)
 214 #define RAMIPS_GDM1_UFRC_P_GDMA1        (1 << 12)
 215 #define RAMIPS_GDM1_UFRC_P_PPE          (6 << 12)
 216
 217 /* checksums */
 218 #define RAMIPS_ICS_GEN_EN               BIT(2)
 219 #define RAMIPS_UCS_GEN_EN               BIT(1)
 220 #define RAMIPS_TCS_GEN_EN               BIT(0)
 221
 222 /* dma ring */
 223 #define RAMIPS_PST_DRX_IDX0             BIT(16)
 224 #define RAMIPS_PST_DTX_IDX3             BIT(3)
 225 #define RAMIPS_PST_DTX_IDX2             BIT(2)
 226 #define RAMIPS_PST_DTX_IDX1             BIT(1)
 227 #define RAMIPS_PST_DTX_IDX0             BIT(0)
 228
 229 #define RAMIPS_TX_WB_DDONE              BIT(6)
 230 #define RAMIPS_RX_DMA_BUSY              BIT(3)
 231 #define RAMIPS_TX_DMA_BUSY              BIT(1)
 232 #define RAMIPS_RX_DMA_EN                BIT(2)
 233 #define RAMIPS_TX_DMA_EN                BIT(0)
 234
 235 #define RAMIPS_PDMA_SIZE_4DWORDS        (0 << 4)
 236 #define RAMIPS_PDMA_SIZE_8DWORDS        (1 << 4)
 237 #define RAMIPS_PDMA_SIZE_16DWORDS       (2 << 4)
 238
 239 #define RAMIPS_US_CYC_CNT_MASK          0xff
 240 #define RAMIPS_US_CYC_CNT_SHIFT         0x8
 241 #define RAMIPS_US_CYC_CNT_DIVISOR       1000000
 242
 243 #define RX_DMA_PLEN0(_x)                (((_x) >> 16) & 0x3fff)
 244 #define RX_DMA_LSO                      BIT(30)
 245 #define RX_DMA_DONE                     BIT(31)
 246
 247 struct ramips_rx_dma {
 248         unsigned int rxd1;
 249         unsigned int rxd2;
 250         unsigned int rxd3;
 251         unsigned int rxd4;
 252 } __packed __aligned(4);
 253
 254 #define TX_DMA_PLEN0_MASK               ((0x3fff) << 16)
 255 #define TX_DMA_PLEN0(_x)                (((_x) & 0x3fff) << 16)
 256 #define TX_DMA_LSO                      BIT(30)
 257 #define TX_DMA_DONE                     BIT(31)
 258 #define TX_DMA_QN(_x)                   ((_x) << 16)
 259 #define TX_DMA_PN(_x)                   ((_x) << 24)
 260 #define TX_DMA_QN_MASK                  TX_DMA_QN(0x7)
 261 #define TX_DMA_PN_MASK                  TX_DMA_PN(0x7)
 262
 263 struct ramips_tx_dma {
 264         unsigned int txd1;
 265         unsigned int txd2;
 266         unsigned int txd3;
 267         unsigned int txd4;
 268 } __packed __aligned(4);
 269
 270 struct raeth_tx_info {
 271         struct ramips_tx_dma    *tx_desc;
 272         struct sk_buff          *tx_skb;
 273 };
 274
 275 struct raeth_rx_info {
 276         struct ramips_rx_dma    *rx_desc;
 277         struct sk_buff          *rx_skb;
 278         dma_addr_t              rx_dma;
 279         unsigned int            pad;
 280 };
 281
 282 struct raeth_int_stats {
 283         unsigned long           rx_delayed;
 284         unsigned long           tx_delayed;
 285         unsigned long           rx_done0;
 286         unsigned long           tx_done0;
 287         unsigned long           tx_done1;
 288         unsigned long           tx_done2;
 289         unsigned long           tx_done3;
 290         unsigned long           rx_coherent;
 291         unsigned long           tx_coherent;
 292
 293         unsigned long           pse_fq_empty;
 294         unsigned long           pse_p0_fc;
 295         unsigned long           pse_p1_fc;
 296         unsigned long           pse_p2_fc;
 297         unsigned long           pse_buf_drop;
 298
 299         unsigned long           total;
 300 };
 301
 302 struct raeth_debug {
 303         struct dentry           *debugfs_dir;
 304
 305         struct raeth_int_stats  int_stats;
 306 };
 307
 308 struct raeth_priv
 309 {
 310         struct raeth_rx_info    *rx_info;
 311         dma_addr_t              rx_desc_dma;
 312         struct tasklet_struct   rx_tasklet;
 313         struct ramips_rx_dma    *rx;
 314
 315         struct raeth_tx_info    *tx_info;
 316         dma_addr_t              tx_desc_dma;
 317         struct tasklet_struct   tx_housekeeping_tasklet;
 318         struct ramips_tx_dma    *tx;
 319
 320         unsigned int            skb_free_idx;
 321
 322         spinlock_t              page_lock;
 323         struct net_device       *netdev;
 324         struct device           *parent;
 325         struct ramips_eth_platform_data *plat;
 326
 327         int                     link;
 328         int                     speed;
 329         int                     duplex;
 330         int                     tx_fc;
 331         int                     rx_fc;
 332
 333         struct mii_bus          *mii_bus;
 334         int                     mii_irq[PHY_MAX_ADDR];
 335         struct phy_device       *phy_dev;
 336         spinlock_t              phy_lock;
 337
 338 #ifdef CONFIG_NET_RAMIPS_DEBUG_FS
 339         struct raeth_debug      debug;
 340 #endif
 341 };
 342
 343 #ifdef CONFIG_NET_RAMIPS_DEBUG_FS
 344 int raeth_debugfs_root_init(void);
 345 void raeth_debugfs_root_exit(void);
 346 int raeth_debugfs_init(struct raeth_priv *re);
 347 void raeth_debugfs_exit(struct raeth_priv *re);
 348 void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status);
 349 #else
 350 static inline int raeth_debugfs_root_init(void) { return 0; }
 351 static inline void raeth_debugfs_root_exit(void) {}
 352 static inline int raeth_debugfs_init(struct raeth_priv *re) { return 0; }
 353 static inline void raeth_debugfs_exit(struct raeth_priv *re) {}
 354 static inline void raeth_debugfs_update_int_stats(struct raeth_priv *re,
 355                                                   u32 status) {}
 356 #endif /* CONFIG_NET_RAMIPS_DEBUG_FS */
 357
 358 #endif /* RAMIPS_ETH_H */