target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/if_vlan.h>
  18 #include <linux/of_net.h>
  19
  20 #include <asm/mach-ralink/ralink_regs.h>
  21
  22 #include <mt7620.h>
  23 #include "mtk_eth_soc.h"
  24 #include "gsw_mt7620.h"
  25 #include "mt7530.h"
  26 #include "mdio.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7620_L4_VALID         BIT(23)
  31
  32 #define MT7620_TX_DMA_UDF       BIT(15)
  33 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  34
  35 #define CDMA_ICS_EN             BIT(2)
  36 #define CDMA_UCS_EN             BIT(1)
  37 #define CDMA_TCS_EN             BIT(0)
  38
  39 #define GDMA_ICS_EN             BIT(22)
  40 #define GDMA_TCS_EN             BIT(21)
  41 #define GDMA_UCS_EN             BIT(20)
  42
  43 /* frame engine counters */
  44 #define MT7620_REG_MIB_OFFSET   0x1000
  45 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  46 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  47 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  48
  49 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  50 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  51
  52 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  53 #define MT7620_FE_INT_STATUS2   (FE_FE_OFFSET + 0x08)
  54
  55 /* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
  56  * but after test it should be BIT(13).
  57  */
  58 #define MT7620_FE_GDM1_AF       BIT(13)
  59
  60 static const u16 mt7620_reg_table[FE_REG_COUNT] = {
  61         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  62         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  63         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  64         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  65         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  66         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  67         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  68         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  69         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  70         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  71         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  72         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  73         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  74         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  75         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  76         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  77         [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
  78 };
  79
  80 static int mt7620_gsw_config(struct fe_priv *priv)
  81 {
  82         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
  83         u32 val;
  84
  85         /* is the mt7530 internal or external */
  86         if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
  87                 mt7530_probe(priv->dev, gsw->base, NULL, 0);
  88                 mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
  89
  90                 /* magic values from original SDK */
  91                 val = mt7530_mdio_r32(gsw, 0x7830);
  92                 val &= ~BIT(0);
  93                 val |= BIT(1);
  94                 mt7530_mdio_w32(gsw, 0x7830, val);
  95
  96                 val = mt7530_mdio_r32(gsw, 0x7a40);
  97                 val &= ~BIT(30);
  98                 mt7530_mdio_w32(gsw, 0x7a40, val);
  99
 100                 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 101
 102                 pr_info("mt7530: mdio central align\n");
 103         } else {
 104                 mt7530_probe(priv->dev, gsw->base, NULL, 1);
 105         }
 106
 107         return 0;
 108 }
 109
 110 static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 111 {
 112         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 113         unsigned long flags;
 114
 115         spin_lock_irqsave(&priv->page_lock, flags);
 116         mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 117         mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 118                 GSW_REG_SMACCR0);
 119         spin_unlock_irqrestore(&priv->page_lock, flags);
 120 }
 121
 122 static void mt7620_auto_poll(struct mt7620_gsw *gsw, int port)
 123 {
 124         int phy;
 125         int lsb = -1, msb = 0;
 126
 127         for_each_set_bit(phy, &gsw->autopoll, 32) {
 128                 if (lsb < 0)
 129                         lsb = phy;
 130                 msb = phy;
 131         }
 132
 133         if (lsb == msb && port ==  4)
 134                 msb++;
 135         else if (lsb == msb && port ==  5)
 136                 lsb--;
 137
 138         mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
 139                 (msb << 8) | lsb, ESW_PHY_POLLING);
 140 }
 141
 142 static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 143 {
 144         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 145         const __be32 *_id = of_get_property(np, "reg", NULL);
 146         const __be32 *phy_addr;
 147         phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
 148         int size, id;
 149         int shift = 12;
 150         u32 val, mask = 0;
 151         u32 val_delay = 0;
 152         u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
 153         int min = (gsw->port4_ephy) ? (5) : (4);
 154
 155         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 156                 if (_id)
 157                         pr_err("%s: invalid port id %d\n", np->name,
 158                                be32_to_cpu(*_id));
 159                 else
 160                         pr_err("%s: invalid port id\n", np->name);
 161                 return;
 162         }
 163
 164         id = be32_to_cpu(*_id);
 165
 166         if (id == 4)
 167                 shift = 14;
 168
 169         priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
 170                                                    &size);
 171         if (priv->phy->phy_fixed[id] &&
 172             (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 173                 pr_err("%s: invalid fixed link property\n", np->name);
 174                 priv->phy->phy_fixed[id] = NULL;
 175         }
 176
 177         of_get_phy_mode(np, &phy_mode);
 178         switch (phy_mode) {
 179         case PHY_INTERFACE_MODE_RGMII:
 180                 mask = 0;
 181                 /* Do not touch rx/tx delay in this state to avoid problems with
 182                  * backward compability.
 183                  */
 184                 mask_delay = 0;
 185                 break;
 186         case PHY_INTERFACE_MODE_RGMII_ID:
 187                 mask = 0;
 188                 val_delay |= GSW_REG_GPCx_TXDELAY;
 189                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 190                 break;
 191         case PHY_INTERFACE_MODE_RGMII_RXID:
 192                 mask = 0;
 193                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 194                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 195                 break;
 196         case PHY_INTERFACE_MODE_RGMII_TXID:
 197                 mask = 0;
 198                 val_delay |= GSW_REG_GPCx_TXDELAY;
 199                 val_delay |= GSW_REG_GPCx_RXDELAY;
 200                 break;
 201         case PHY_INTERFACE_MODE_MII:
 202                 mask = 1;
 203                 break;
 204         case PHY_INTERFACE_MODE_RMII:
 205                 mask = 2;
 206                 break;
 207         default:
 208                 dev_err(priv->dev, "port %d - invalid phy mode\n", id);
 209                 return;
 210         }
 211
 212         val = rt_sysc_r32(SYSC_REG_CFG1);
 213         val &= ~(3 << shift);
 214         val |= mask << shift;
 215         rt_sysc_w32(val, SYSC_REG_CFG1);
 216
 217         if (id == 4) {
 218                 val = mtk_switch_r32(gsw, GSW_REG_GPC2);
 219                 val &= ~(mask_delay);
 220                 val |= val_delay & mask_delay;
 221                 mtk_switch_w32(gsw, val, GSW_REG_GPC2);
 222         }
 223         else if (id == 5) {
 224                 val = mtk_switch_r32(gsw, GSW_REG_GPC1);
 225                 val &= ~(mask_delay);
 226                 val |= val_delay & mask_delay;
 227                 mtk_switch_w32(gsw, val, GSW_REG_GPC1);
 228         }
 229
 230         if (priv->phy->phy_fixed[id]) {
 231                 const __be32 *link = priv->phy->phy_fixed[id];
 232                 int tx_fc, rx_fc;
 233                 u32 val = 0;
 234
 235                 priv->phy->speed[id] = be32_to_cpup(link++);
 236                 tx_fc = be32_to_cpup(link++);
 237                 rx_fc = be32_to_cpup(link++);
 238                 priv->phy->duplex[id] = be32_to_cpup(link++);
 239                 priv->link[id] = 1;
 240
 241                 switch (priv->phy->speed[id]) {
 242                 case SPEED_10:
 243                         val = 0;
 244                         break;
 245                 case SPEED_100:
 246                         val = 1;
 247                         break;
 248                 case SPEED_1000:
 249                         val = 2;
 250                         break;
 251                 default:
 252                         dev_err(priv->dev, "port %d - invalid link speed: %d\n",
 253                                 id, priv->phy->speed[id]);
 254                         priv->phy->phy_fixed[id] = 0;
 255                         return;
 256                 }
 257                 val = PMCR_SPEED(val);
 258                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 259                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 260                 if (tx_fc)
 261                         val |= PMCR_TX_FC;
 262                 if (rx_fc)
 263                         val |= PMCR_RX_FC;
 264                 if (priv->phy->duplex[id])
 265                         val |= PMCR_DUPLEX;
 266                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 267                 dev_info(priv->dev, "port %d - using fixed link parameters\n", id);
 268                 return;
 269         }
 270
 271         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 272         if (!priv->phy->phy_node[id]) {
 273                 dev_err(priv->dev, "port %d - missing phy handle\n", id);
 274                 return;
 275         }
 276
 277         phy_addr = of_get_property(priv->phy->phy_node[id], "reg", NULL);
 278         if (phy_addr && mdiobus_get_phy(priv->mii_bus, be32_to_cpup(phy_addr))) {
 279                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 280                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 281
 282                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 283                 fe_connect_phy_node(priv, priv->phy->phy_node[id], id);
 284                 gsw->autopoll |= BIT(be32_to_cpup(phy_addr));
 285                 mt7620_auto_poll(gsw,id);
 286         }
 287 }
 288
 289 static void mt7620_fe_reset(struct fe_priv *priv)
 290 {
 291         fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 292 }
 293
 294 static void mt7620_rxcsum_config(bool enable)
 295 {
 296         if (enable)
 297                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 298                                         GDMA_TCS_EN | GDMA_UCS_EN),
 299                                 MT7620A_GDMA1_FWD_CFG);
 300         else
 301                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 302                                         GDMA_TCS_EN | GDMA_UCS_EN),
 303                                 MT7620A_GDMA1_FWD_CFG);
 304 }
 305
 306 static void mt7620_txcsum_config(bool enable)
 307 {
 308         if (enable)
 309                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 310                                         CDMA_UCS_EN | CDMA_TCS_EN),
 311                                 MT7620A_CDMA_CSG_CFG);
 312         else
 313                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 314                                         CDMA_UCS_EN | CDMA_TCS_EN),
 315                                 MT7620A_CDMA_CSG_CFG);
 316 }
 317
 318 static int mt7620_fwd_config(struct fe_priv *priv)
 319 {
 320         struct net_device *dev = priv_netdev(priv);
 321
 322         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 323
 324         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 325         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 326
 327         return 0;
 328 }
 329
 330 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 331 {
 332 }
 333
 334 static void mt7620_init_data(struct fe_soc_data *data,
 335                              struct net_device *netdev)
 336 {
 337         struct fe_priv *priv = netdev_priv(netdev);
 338
 339         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 340                 FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
 341
 342         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 343                 NETIF_F_HW_VLAN_CTAG_TX;
 344         if (mt7620_get_eco() >= 5)
 345                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 346                         NETIF_F_IPV6_CSUM;
 347 }
 348
 349 static struct fe_soc_data mt7620_data = {
 350         .init_data = mt7620_init_data,
 351         .reset_fe = mt7620_fe_reset,
 352         .set_mac = mt7620_set_mac,
 353         .fwd_config = mt7620_fwd_config,
 354         .tx_dma = mt7620_tx_dma,
 355         .switch_init = mtk_gsw_init,
 356         .switch_config = mt7620_gsw_config,
 357         .port_init = mt7620_port_init,
 358         .reg_table = mt7620_reg_table,
 359         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 360         .rx_int = RT5350_RX_DONE_INT,
 361         .tx_int = RT5350_TX_DONE_INT,
 362         .status_int = MT7620_FE_GDM1_AF,
 363         .checksum_bit = MT7620_L4_VALID,
 364         .has_carrier = mt7620_has_carrier,
 365         .mdio_read = mt7620_mdio_read,
 366         .mdio_write = mt7620_mdio_write,
 367         .mdio_adjust_link = mt7620_mdio_link_adjust,
 368 };
 369
 370 const struct of_device_id of_fe_match[] = {
 371         { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
 372         {},
 373 };
 374
 375 MODULE_DEVICE_TABLE(of, of_fe_match);