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ramips: mt7530 swconfig: fix race condition in register access
[openwrt/staging/jow.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / mt7530.c
1 /*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
13 * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
14 */
15
16 #include <linux/if.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/bitops.h>
25 #include <net/genetlink.h>
26 #include <linux/switch.h>
27 #include <linux/delay.h>
28 #include <linux/phy.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/lockdep.h>
32 #include <linux/workqueue.h>
33 #include <linux/of_device.h>
34 #include <asm/byteorder.h>
35
36 #include "mt7530.h"
37
38 #define MT7530_CPU_PORT 6
39 #define MT7530_NUM_PORTS 8
40 #define MT7530_NUM_VLANS 16
41 #define MT7530_MAX_VID 4095
42 #define MT7530_MIN_VID 0
43 #define MT7530_NUM_ARL_RECORDS 2048
44 #define ARL_LINE_LENGTH 30
45
46 #define MT7530_PORT_MIB_TXB_ID 2 /* TxGOC */
47 #define MT7530_PORT_MIB_RXB_ID 6 /* RxGOC */
48
49 /* registers */
50 #define REG_ESW_WT_MAC_MFC 0x10
51
52 #define REG_ESW_WT_MAC_MFC_MIRROR_ENABLE BIT(3)
53 #define REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK 0x07
54
55 #define REG_ESW_VLAN_VTCR 0x90
56 #define REG_ESW_VLAN_VAWD1 0x94
57 #define REG_ESW_VLAN_VAWD2 0x98
58 #define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
59
60 #define REG_ESW_WT_MAC_ATC 0x80
61 #define REG_ESW_TABLE_ATRD 0x8C
62 #define REG_ESW_TABLE_TSRA1 0x84
63 #define REG_ESW_TABLE_TSRA2 0x88
64
65 #define REG_MAC_ATC_START 0x8004
66 #define REG_MAC_ATC_NEXT 0x8005
67
68 #define REG_MAC_ATC_BUSY 0x8000U
69 #define REG_MAC_ATC_SRCH_HIT 0x2000U
70 #define REG_MAC_ATC_SRCH_END 0x4000U
71 #define REG_ATRD_VALID 0xff000000U
72 #define REG_ATRD_PORT_MASK 0xff0U
73
74 #define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
75 #define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
76 #define REG_ESW_VLAN_VAWD1_VALID BIT(0)
77
78 /* vlan egress mode */
79 enum {
80 ETAG_CTRL_UNTAG = 0,
81 ETAG_CTRL_TAG = 2,
82 ETAG_CTRL_SWAP = 1,
83 ETAG_CTRL_STACK = 3,
84 };
85
86 #define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
87 #define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
88 #define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
89
90 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT BIT(8)
91 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT BIT(9)
92 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_MASK 0x0100
93 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_MASK 0x0200
94
95 #define REG_HWTRAP 0x7804
96
97 #define MIB_DESC(_s , _o, _n) \
98 { \
99 .size = (_s), \
100 .offset = (_o), \
101 .name = (_n), \
102 }
103
104 struct mt7xxx_mib_desc {
105 unsigned int size;
106 unsigned int offset;
107 const char *name;
108 };
109
110 static const struct mt7xxx_mib_desc mt7620_mibs[] = {
111 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
112 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
113 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
114 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
115 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
116 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
117 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
118 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
119 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
120 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
121 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
122 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
123 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
124 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
125 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
126 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
127 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
128 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
129 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
130 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
131 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
132 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
133 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
134 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
135 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
136 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
137 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
138 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
139 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
140 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
141 };
142
143 static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
144 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
145 MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
146 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
147 MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
148 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
149 MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
150 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
151 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
152 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
153 };
154
155 enum {
156 /* Global attributes. */
157 MT7530_ATTR_ENABLE_VLAN,
158 };
159
160 struct mt7530_port_entry {
161 u16 pvid;
162 bool mirror_rx;
163 bool mirror_tx;
164 };
165
166 struct mt7530_vlan_entry {
167 u16 vid;
168 u8 member;
169 u8 etags;
170 };
171
172 struct mt7530_priv {
173 void __iomem *base;
174 struct mii_bus *bus;
175 struct switch_dev swdev;
176
177 u8 mirror_dest_port;
178 bool global_vlan_enable;
179 struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
180 struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
181 char arl_buf[MT7530_NUM_ARL_RECORDS * ARL_LINE_LENGTH + 1];
182 };
183
184 struct mt7530_mapping {
185 char *name;
186 u16 pvids[MT7530_NUM_PORTS];
187 u8 members[MT7530_NUM_VLANS];
188 u8 etags[MT7530_NUM_VLANS];
189 u16 vids[MT7530_NUM_VLANS];
190 } mt7530_defaults[] = {
191 {
192 .name = "llllw",
193 .pvids = { 1, 1, 1, 1, 2, 1, 1 },
194 .members = { 0, 0x6f, 0x50 },
195 .etags = { 0, 0x40, 0x40 },
196 .vids = { 0, 1, 2 },
197 }, {
198 .name = "wllll",
199 .pvids = { 2, 1, 1, 1, 1, 1, 1 },
200 .members = { 0, 0x7e, 0x41 },
201 .etags = { 0, 0x40, 0x40 },
202 .vids = { 0, 1, 2 },
203 }, {
204 .name = "lwlll",
205 .pvids = { 1, 2, 1, 1, 1, 1, 1 },
206 .members = { 0, 0x7d, 0x42 },
207 .etags = { 0, 0x40, 0x40 },
208 .vids = { 0, 1, 2 },
209 },
210 };
211
212 struct mt7530_mapping*
213 mt7530_find_mapping(struct device_node *np)
214 {
215 const char *map;
216 int i;
217
218 if (of_property_read_string(np, "mediatek,portmap", &map))
219 return NULL;
220
221 for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
222 if (!strcmp(map, mt7530_defaults[i].name))
223 return &mt7530_defaults[i];
224
225 return NULL;
226 }
227
228 static void
229 mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
230 {
231 int i = 0;
232
233 for (i = 0; i < MT7530_NUM_PORTS; i++)
234 mt7530->port_entries[i].pvid = map->pvids[i];
235
236 for (i = 0; i < MT7530_NUM_VLANS; i++) {
237 mt7530->vlan_entries[i].member = map->members[i];
238 mt7530->vlan_entries[i].etags = map->etags[i];
239 mt7530->vlan_entries[i].vid = map->vids[i];
240 }
241 }
242
243 static int
244 mt7530_reset_switch(struct switch_dev *dev)
245 {
246 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
247 int i;
248
249 memset(priv->port_entries, 0, sizeof(priv->port_entries));
250 memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
251
252 /* set default vid of each vlan to the same number of vlan, so the vid
253 * won't need be set explicitly.
254 */
255 for (i = 0; i < MT7530_NUM_VLANS; i++) {
256 priv->vlan_entries[i].vid = i;
257 }
258
259 return 0;
260 }
261
262 static int
263 mt7530_get_vlan_enable(struct switch_dev *dev,
264 const struct switch_attr *attr,
265 struct switch_val *val)
266 {
267 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
268
269 val->value.i = priv->global_vlan_enable;
270
271 return 0;
272 }
273
274 static int
275 mt7530_set_vlan_enable(struct switch_dev *dev,
276 const struct switch_attr *attr,
277 struct switch_val *val)
278 {
279 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
280
281 priv->global_vlan_enable = val->value.i != 0;
282
283 return 0;
284 }
285
286 static u32
287 mt7530_r32(struct mt7530_priv *priv, u32 reg)
288 {
289 u32 val;
290 if (priv->bus) {
291 u16 high, low;
292
293 mutex_lock(&priv->bus->mdio_lock);
294 __mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
295 low = __mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
296 high = __mdiobus_read(priv->bus, 0x1f, 0x10);
297 mutex_unlock(&priv->bus->mdio_lock);
298
299 return (high << 16) | (low & 0xffff);
300 }
301
302 val = ioread32(priv->base + reg);
303 pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
304
305 return val;
306 }
307
308 static void
309 mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
310 {
311 if (priv->bus) {
312 mutex_lock(&priv->bus->mdio_lock);
313 __mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
314 __mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
315 __mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
316 mutex_unlock(&priv->bus->mdio_lock);
317 return;
318 }
319
320 pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
321 iowrite32(val, priv->base + reg);
322 }
323
324 static void
325 mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
326 {
327 int i;
328
329 mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
330
331 for (i = 0; i < 20; i++) {
332 u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
333
334 if ((val & BIT(31)) == 0)
335 break;
336
337 udelay(1000);
338 }
339 if (i == 20)
340 printk("mt7530: vtcr timeout\n");
341 }
342
343 static int
344 mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
345 {
346 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
347
348 if (port >= MT7530_NUM_PORTS)
349 return -EINVAL;
350
351 *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
352 *val &= 0xfff;
353
354 return 0;
355 }
356
357 static int
358 mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
359 {
360 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
361
362 if (port >= MT7530_NUM_PORTS)
363 return -EINVAL;
364
365 if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
366 return -EINVAL;
367
368 priv->port_entries[port].pvid = pvid;
369
370 return 0;
371 }
372
373 static int
374 mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
375 {
376 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
377 u32 member;
378 u32 etags;
379 int i;
380
381 val->len = 0;
382
383 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
384 return -EINVAL;
385
386 mt7530_vtcr(priv, 0, val->port_vlan);
387
388 member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
389 member >>= 16;
390 member &= 0xff;
391
392 etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
393
394 for (i = 0; i < MT7530_NUM_PORTS; i++) {
395 struct switch_port *p;
396 int etag;
397
398 if (!(member & BIT(i)))
399 continue;
400
401 p = &val->value.ports[val->len++];
402 p->id = i;
403
404 etag = (etags >> (i * 2)) & 0x3;
405
406 if (etag == ETAG_CTRL_TAG)
407 p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
408 else if (etag != ETAG_CTRL_UNTAG)
409 printk("vlan %d port %d egress tag control neither untag nor tag: %d.\n",
410 val->port_vlan, i, etag);
411 }
412
413 return 0;
414 }
415
416 static int
417 mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
418 {
419 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
420 u8 member = 0;
421 u8 etags = 0;
422 int i;
423
424 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
425 val->len > MT7530_NUM_PORTS)
426 return -EINVAL;
427
428 for (i = 0; i < val->len; i++) {
429 struct switch_port *p = &val->value.ports[i];
430
431 if (p->id >= MT7530_NUM_PORTS)
432 return -EINVAL;
433
434 member |= BIT(p->id);
435
436 if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
437 etags |= BIT(p->id);
438 }
439 priv->vlan_entries[val->port_vlan].member = member;
440 priv->vlan_entries[val->port_vlan].etags = etags;
441
442 return 0;
443 }
444
445 static int
446 mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
447 struct switch_val *val)
448 {
449 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
450 int vlan;
451 u16 vid;
452
453 vlan = val->port_vlan;
454 vid = (u16)val->value.i;
455
456 if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
457 return -EINVAL;
458
459 if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
460 return -EINVAL;
461
462 priv->vlan_entries[vlan].vid = vid;
463 return 0;
464 }
465
466 static int
467 mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
468 struct switch_val *val)
469 {
470 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
471 u32 vid;
472 int vlan;
473
474 vlan = val->port_vlan;
475
476 vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
477 if (vlan & 1)
478 vid = vid >> 12;
479 vid &= 0xfff;
480
481 val->value.i = vid;
482 return 0;
483 }
484
485 static int
486 mt7530_get_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,
487 struct switch_val *val)
488 {
489 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
490
491 val->value.i = priv->mirror_dest_port;
492
493 return 0;
494 }
495
496 static int
497 mt7530_set_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,
498 struct switch_val *val)
499 {
500 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
501
502 priv->mirror_dest_port = val->value.i;
503
504 return 0;
505 }
506
507 static int
508 mt7530_get_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
509 struct switch_val *val)
510 {
511 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
512
513 val->value.i = priv->port_entries[val->port_vlan].mirror_rx;
514
515 return 0;
516 }
517
518 static int
519 mt7530_set_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
520 struct switch_val *val)
521 {
522 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
523
524 priv->port_entries[val->port_vlan].mirror_rx = val->value.i;
525
526 return 0;
527 }
528
529 static int
530 mt7530_get_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
531 struct switch_val *val)
532 {
533 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
534
535 val->value.i = priv->port_entries[val->port_vlan].mirror_tx;
536
537 return 0;
538 }
539
540 static int
541 mt7530_set_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
542 struct switch_val *val)
543 {
544 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
545
546 priv->port_entries[val->port_vlan].mirror_tx = val->value.i;
547
548 return 0;
549 }
550
551 static void
552 mt7530_write_vlan_entry(struct mt7530_priv *priv, int vlan, u16 vid,
553 u8 ports, u8 etags)
554 {
555 int port;
556 u32 val;
557
558 /* vid of vlan */
559 val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
560 if (vlan % 2 == 0) {
561 val &= 0xfff000;
562 val |= vid;
563 } else {
564 val &= 0xfff;
565 val |= (vid << 12);
566 }
567 mt7530_w32(priv, REG_ESW_VLAN_VTIM(vlan), val);
568
569 /* vlan port membership */
570 if (ports)
571 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
572 REG_ESW_VLAN_VAWD1_VTAG_EN | (ports << 16) |
573 REG_ESW_VLAN_VAWD1_VALID);
574 else
575 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
576
577 /* egress mode */
578 val = 0;
579 for (port = 0; port < MT7530_NUM_PORTS; port++) {
580 if (etags & BIT(port))
581 val |= ETAG_CTRL_TAG << (port * 2);
582 else
583 val |= ETAG_CTRL_UNTAG << (port * 2);
584 }
585 mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
586
587 /* write to vlan table */
588 mt7530_vtcr(priv, 1, vlan);
589 }
590
591 static int
592 mt7530_apply_config(struct switch_dev *dev)
593 {
594 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
595 int i, j;
596 u8 tag_ports;
597 u8 untag_ports;
598 bool is_mirror = false;
599
600 if (!priv->global_vlan_enable) {
601 for (i = 0; i < MT7530_NUM_PORTS; i++)
602 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
603
604 mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
605
606 for (i = 0; i < MT7530_NUM_PORTS; i++)
607 mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
608
609 return 0;
610 }
611
612 /* set all ports as security mode */
613 for (i = 0; i < MT7530_NUM_PORTS; i++)
614 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
615
616 /* check if a port is used in tag/untag vlan egress mode */
617 tag_ports = 0;
618 untag_ports = 0;
619
620 for (i = 0; i < MT7530_NUM_VLANS; i++) {
621 u8 member = priv->vlan_entries[i].member;
622 u8 etags = priv->vlan_entries[i].etags;
623
624 if (!member)
625 continue;
626
627 for (j = 0; j < MT7530_NUM_PORTS; j++) {
628 if (!(member & BIT(j)))
629 continue;
630
631 if (etags & BIT(j))
632 tag_ports |= 1u << j;
633 else
634 untag_ports |= 1u << j;
635 }
636 }
637
638 /* set all untag-only ports as transparent and the rest as user port */
639 for (i = 0; i < MT7530_NUM_PORTS; i++) {
640 u32 pvc_mode = 0x81000000;
641
642 if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
643 pvc_mode = 0x810000c0;
644
645 mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
646 }
647
648 /* first clear the swtich vlan table */
649 for (i = 0; i < MT7530_NUM_VLANS; i++)
650 mt7530_write_vlan_entry(priv, i, i, 0, 0);
651
652 /* now program only vlans with members to avoid
653 clobbering remapped entries in later iterations */
654 for (i = 0; i < MT7530_NUM_VLANS; i++) {
655 u16 vid = priv->vlan_entries[i].vid;
656 u8 member = priv->vlan_entries[i].member;
657 u8 etags = priv->vlan_entries[i].etags;
658
659 if (member)
660 mt7530_write_vlan_entry(priv, i, vid, member, etags);
661 }
662
663 /* Port Default PVID */
664 for (i = 0; i < MT7530_NUM_PORTS; i++) {
665 int vlan = priv->port_entries[i].pvid;
666 u16 pvid = 0;
667 u32 val;
668
669 if (vlan < MT7530_NUM_VLANS && priv->vlan_entries[vlan].member)
670 pvid = priv->vlan_entries[vlan].vid;
671
672 val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
673 val &= ~0xfff;
674 val |= pvid;
675 mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
676 }
677
678 /* set mirroring source port */
679 for (i = 0; i < MT7530_NUM_PORTS; i++) {
680 u32 val = mt7530_r32(priv, REG_ESW_PORT_PCR(i));
681 if (priv->port_entries[i].mirror_rx) {
682 val |= REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT;
683 is_mirror = true;
684 }
685
686 if (priv->port_entries[i].mirror_tx) {
687 val |= REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT;
688 is_mirror = true;
689 }
690
691 mt7530_w32(priv, REG_ESW_PORT_PCR(i), val);
692 }
693
694 /* set mirroring monitor port */
695 if (is_mirror) {
696 u32 val = mt7530_r32(priv, REG_ESW_WT_MAC_MFC);
697 val |= REG_ESW_WT_MAC_MFC_MIRROR_ENABLE;
698 val &= ~REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK;
699 val |= priv->mirror_dest_port;
700 mt7530_w32(priv, REG_ESW_WT_MAC_MFC, val);
701 }
702
703 return 0;
704 }
705
706 static int
707 mt7530_get_port_link(struct switch_dev *dev, int port,
708 struct switch_port_link *link)
709 {
710 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
711 u32 speed, pmsr;
712
713 if (port < 0 || port >= MT7530_NUM_PORTS)
714 return -EINVAL;
715
716 pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
717
718 link->link = pmsr & 1;
719 link->duplex = (pmsr >> 1) & 1;
720 speed = (pmsr >> 2) & 3;
721
722 switch (speed) {
723 case 0:
724 link->speed = SWITCH_PORT_SPEED_10;
725 break;
726 case 1:
727 link->speed = SWITCH_PORT_SPEED_100;
728 break;
729 case 2:
730 case 3: /* forced gige speed can be 2 or 3 */
731 link->speed = SWITCH_PORT_SPEED_1000;
732 break;
733 default:
734 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
735 break;
736 }
737
738 return 0;
739 }
740
741 static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
742 {
743 return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
744 }
745
746 static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
747 {
748 return mt7530_r32(priv,
749 MT7620_MIB_COUNTER_BASE_PORT +
750 (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
751 mt7620_port_mibs[i].offset);
752 }
753
754 static int mt7530_sw_get_mib(struct switch_dev *dev,
755 const struct switch_attr *attr,
756 struct switch_val *val)
757 {
758 static char buf[4096];
759 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
760 int i, len = 0;
761
762 len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
763
764 for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
765 u64 counter;
766 len += snprintf(buf + len, sizeof(buf) - len,
767 "%-11s: ", mt7620_mibs[i].name);
768 counter = get_mib_counter_7620(priv, i);
769 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
770 counter);
771 }
772
773 val->value.s = buf;
774 val->len = len;
775 return 0;
776 }
777
778 static char *mt7530_print_arl_table_row(u32 atrd,
779 u32 mac1,
780 u32 mac2,
781 char *buf,
782 size_t *size)
783 {
784 int ret;
785 size_t port;
786 size_t i;
787 u8 port_map;
788 u8 mac[ETH_ALEN];
789
790 mac1 = ntohl(mac1);
791 mac2 = ntohl(mac2);
792 port_map = (u8)((atrd & REG_ATRD_PORT_MASK) >> 4);
793 memcpy(mac, &mac1, sizeof(mac1));
794 memcpy(mac + sizeof(mac1), &mac2, sizeof(mac) - sizeof(mac1));
795 for (port = 0, i = 1; port < MT7530_NUM_PORTS; ++port, i <<= 1) {
796 if (port_map & i) {
797 ret = snprintf(buf, *size, "Port %d: MAC %pM\n", port, mac);
798 if (ret >= *size || ret <= 0) {
799 *buf = 0;
800 buf = NULL;
801 goto out;
802 }
803 buf += ret;
804 *size = *size - ret;
805 }
806 }
807 out:
808 return buf;
809 }
810
811 static int mt7530_get_arl_table(struct switch_dev *dev,
812 const struct switch_attr *attr,
813 struct switch_val *val)
814 {
815 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
816 char *buf = priv->arl_buf;
817 size_t size = sizeof(priv->arl_buf);
818 size_t count = 0;
819 size_t retry_times = 100;
820 int ret;
821 u32 atc;
822
823 ret = snprintf(buf, size, "address resolution table\n");
824 if (ret >= size || ret <= 0) {
825 priv->arl_buf[0] = 0;
826 goto out;
827 }
828 buf += ret;
829 size = size - ret;
830
831 mt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_START);
832
833 do {
834 atc = mt7530_r32(priv, REG_ESW_WT_MAC_ATC);
835 if (atc & REG_MAC_ATC_SRCH_HIT && !(atc & REG_MAC_ATC_BUSY)) {
836 u32 atrd;
837
838 ++count;
839 atrd = mt7530_r32(priv, REG_ESW_TABLE_ATRD);
840 if (atrd & REG_ATRD_VALID) {
841 u32 mac1;
842 u32 mac2;
843
844 mac1 = mt7530_r32(priv, REG_ESW_TABLE_TSRA1);
845 mac2 = mt7530_r32(priv, REG_ESW_TABLE_TSRA2);
846
847 if (!(atc & REG_MAC_ATC_SRCH_END))
848 mt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_NEXT);
849
850 buf = mt7530_print_arl_table_row(atrd, mac1, mac2, buf, &size);
851 if (!buf) {
852 pr_warn("%s: too many addresses\n", __func__);
853 goto out;
854 }
855 } else if (!(atc & REG_MAC_ATC_SRCH_END)) {
856 mt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_NEXT);
857 }
858 } else {
859 --retry_times;
860 usleep_range(1000, 5000);
861 }
862 } while (!(atc & REG_MAC_ATC_SRCH_END) &&
863 count < MT7530_NUM_ARL_RECORDS &&
864 retry_times > 0);
865 out:
866 val->value.s = priv->arl_buf;
867 val->len = strlen(priv->arl_buf);
868
869 return 0;
870 }
871
872 static int mt7530_sw_get_port_mib(struct switch_dev *dev,
873 const struct switch_attr *attr,
874 struct switch_val *val)
875 {
876 static char buf[4096];
877 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
878 int i, len = 0;
879
880 if (val->port_vlan >= MT7530_NUM_PORTS)
881 return -EINVAL;
882
883 len += snprintf(buf + len, sizeof(buf) - len,
884 "Port %d MIB counters\n", val->port_vlan);
885
886 for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
887 u64 counter;
888 len += snprintf(buf + len, sizeof(buf) - len,
889 "%-11s: ", mt7620_port_mibs[i].name);
890 counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
891 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
892 counter);
893 }
894
895 val->value.s = buf;
896 val->len = len;
897 return 0;
898 }
899
900 static int mt7530_get_port_stats(struct switch_dev *dev, int port,
901 struct switch_port_stats *stats)
902 {
903 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
904
905 if (port < 0 || port >= MT7530_NUM_PORTS)
906 return -EINVAL;
907
908 stats->tx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_TXB_ID, port);
909 stats->rx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_RXB_ID, port);
910
911 return 0;
912 }
913
914 static const struct switch_attr mt7530_global[] = {
915 {
916 .type = SWITCH_TYPE_INT,
917 .name = "enable_vlan",
918 .description = "VLAN mode (1:enabled)",
919 .max = 1,
920 .id = MT7530_ATTR_ENABLE_VLAN,
921 .get = mt7530_get_vlan_enable,
922 .set = mt7530_set_vlan_enable,
923 }, {
924 .type = SWITCH_TYPE_STRING,
925 .name = "mib",
926 .description = "Get MIB counters for switch",
927 .get = mt7530_sw_get_mib,
928 .set = NULL,
929 }, {
930 .type = SWITCH_TYPE_INT,
931 .name = "mirror_monitor_port",
932 .description = "Mirror monitor port",
933 .set = mt7530_set_mirror_monitor_port,
934 .get = mt7530_get_mirror_monitor_port,
935 .max = MT7530_NUM_PORTS - 1
936 },
937 {
938 .type = SWITCH_TYPE_STRING,
939 .name = "arl_table",
940 .description = "Get ARL table",
941 .set = NULL,
942 .get = mt7530_get_arl_table,
943 },
944 };
945
946 static const struct switch_attr mt7530_port[] = {
947 {
948 .type = SWITCH_TYPE_STRING,
949 .name = "mib",
950 .description = "Get MIB counters for port",
951 .get = mt7530_sw_get_port_mib,
952 .set = NULL,
953 }, {
954 .type = SWITCH_TYPE_INT,
955 .name = "enable_mirror_rx",
956 .description = "Enable mirroring of RX packets",
957 .set = mt7530_set_port_mirror_rx,
958 .get = mt7530_get_port_mirror_rx,
959 .max = 1,
960 }, {
961 .type = SWITCH_TYPE_INT,
962 .name = "enable_mirror_tx",
963 .description = "Enable mirroring of TX packets",
964 .set = mt7530_set_port_mirror_tx,
965 .get = mt7530_get_port_mirror_tx,
966 .max = 1,
967 },
968 };
969
970 static const struct switch_attr mt7530_vlan[] = {
971 {
972 .type = SWITCH_TYPE_INT,
973 .name = "vid",
974 .description = "VLAN ID (0-4094)",
975 .set = mt7530_set_vid,
976 .get = mt7530_get_vid,
977 .max = 4094,
978 },
979 };
980
981 static const struct switch_dev_ops mt7530_ops = {
982 .attr_global = {
983 .attr = mt7530_global,
984 .n_attr = ARRAY_SIZE(mt7530_global),
985 },
986 .attr_port = {
987 .attr = mt7530_port,
988 .n_attr = ARRAY_SIZE(mt7530_port),
989 },
990 .attr_vlan = {
991 .attr = mt7530_vlan,
992 .n_attr = ARRAY_SIZE(mt7530_vlan),
993 },
994 .get_vlan_ports = mt7530_get_vlan_ports,
995 .set_vlan_ports = mt7530_set_vlan_ports,
996 .get_port_pvid = mt7530_get_port_pvid,
997 .set_port_pvid = mt7530_set_port_pvid,
998 .get_port_link = mt7530_get_port_link,
999 .get_port_stats = mt7530_get_port_stats,
1000 .apply_config = mt7530_apply_config,
1001 .reset_switch = mt7530_reset_switch,
1002 };
1003
1004 int
1005 mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
1006 {
1007 struct switch_dev *swdev;
1008 struct mt7530_priv *mt7530;
1009 struct mt7530_mapping *map;
1010 int ret;
1011
1012 mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
1013 if (!mt7530)
1014 return -ENOMEM;
1015
1016 mt7530->base = base;
1017 mt7530->bus = bus;
1018 mt7530->global_vlan_enable = vlan;
1019
1020 swdev = &mt7530->swdev;
1021 if (bus) {
1022 swdev->alias = "mt7530";
1023 swdev->name = "mt7530";
1024 } else {
1025 swdev->alias = "mt7620";
1026 swdev->name = "mt7620";
1027 }
1028 swdev->cpu_port = MT7530_CPU_PORT;
1029 swdev->ports = MT7530_NUM_PORTS;
1030 swdev->vlans = MT7530_NUM_VLANS;
1031 swdev->ops = &mt7530_ops;
1032
1033 ret = register_switch(swdev, NULL);
1034 if (ret) {
1035 dev_err(dev, "failed to register mt7530\n");
1036 return ret;
1037 }
1038
1039
1040 map = mt7530_find_mapping(dev->of_node);
1041 if (map)
1042 mt7530_apply_mapping(mt7530, map);
1043 mt7530_apply_config(swdev);
1044
1045 /* magic vodoo */
1046 if (bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
1047 dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
1048 mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
1049 }
1050 dev_info(dev, "loaded %s driver\n", swdev->name);
1051
1052 return 0;
1053 }
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