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ramips: ethernet: ralink: use the reset controller api for esw & ephy
[openwrt/staging/dedeckeh.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3050.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22
23 #include <linux/switch.h>
24 #include <linux/reset.h>
25
26 #include "mtk_eth_soc.h"
27
28 /* HW limitations for this switch:
29 * - No large frame support (PKT_MAX_LEN at most 1536)
30 * - Can't have untagged vlan and tagged vlan on one port at the same time,
31 * though this might be possible using the undocumented PPE.
32 */
33
34 #define RT305X_ESW_REG_ISR 0x00
35 #define RT305X_ESW_REG_IMR 0x04
36 #define RT305X_ESW_REG_FCT0 0x08
37 #define RT305X_ESW_REG_PFC1 0x14
38 #define RT305X_ESW_REG_ATS 0x24
39 #define RT305X_ESW_REG_ATS0 0x28
40 #define RT305X_ESW_REG_ATS1 0x2c
41 #define RT305X_ESW_REG_ATS2 0x30
42 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
43 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
44 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
45 #define RT305X_ESW_REG_POA 0x80
46 #define RT305X_ESW_REG_FPA 0x84
47 #define RT305X_ESW_REG_SOCPC 0x8c
48 #define RT305X_ESW_REG_POC0 0x90
49 #define RT305X_ESW_REG_POC1 0x94
50 #define RT305X_ESW_REG_POC2 0x98
51 #define RT305X_ESW_REG_SGC 0x9c
52 #define RT305X_ESW_REG_STRT 0xa0
53 #define RT305X_ESW_REG_PCR0 0xc0
54 #define RT305X_ESW_REG_PCR1 0xc4
55 #define RT305X_ESW_REG_FPA2 0xc8
56 #define RT305X_ESW_REG_FCT2 0xcc
57 #define RT305X_ESW_REG_SGC2 0xe4
58 #define RT305X_ESW_REG_P0LED 0xa4
59 #define RT305X_ESW_REG_P1LED 0xa8
60 #define RT305X_ESW_REG_P2LED 0xac
61 #define RT305X_ESW_REG_P3LED 0xb0
62 #define RT305X_ESW_REG_P4LED 0xb4
63 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
64 #define RT305X_ESW_REG_P1PC 0xec
65 #define RT305X_ESW_REG_P2PC 0xf0
66 #define RT305X_ESW_REG_P3PC 0xf4
67 #define RT305X_ESW_REG_P4PC 0xf8
68 #define RT305X_ESW_REG_P5PC 0xfc
69
70 #define RT305X_ESW_LED_LINK 0
71 #define RT305X_ESW_LED_100M 1
72 #define RT305X_ESW_LED_DUPLEX 2
73 #define RT305X_ESW_LED_ACTIVITY 3
74 #define RT305X_ESW_LED_COLLISION 4
75 #define RT305X_ESW_LED_LINKACT 5
76 #define RT305X_ESW_LED_DUPLCOLL 6
77 #define RT305X_ESW_LED_10MACT 7
78 #define RT305X_ESW_LED_100MACT 8
79 /* Additional led states not in datasheet: */
80 #define RT305X_ESW_LED_BLINK 10
81 #define RT305X_ESW_LED_ON 12
82
83 #define RT305X_ESW_LINK_S 25
84 #define RT305X_ESW_DUPLEX_S 9
85 #define RT305X_ESW_SPD_S 0
86
87 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
88 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
89 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
90
91 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
92
93 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
94 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
95
96 #define RT305X_ESW_PVIDC_PVID_M 0xfff
97 #define RT305X_ESW_PVIDC_PVID_S 12
98
99 #define RT305X_ESW_VLANI_VID_M 0xfff
100 #define RT305X_ESW_VLANI_VID_S 12
101
102 #define RT305X_ESW_VMSC_MSC_M 0xff
103 #define RT305X_ESW_VMSC_MSC_S 8
104
105 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
106 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
107 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
108 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
109
110 #define RT305X_ESW_POC0_EN_BP_S 0
111 #define RT305X_ESW_POC0_EN_FC_S 8
112 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
113 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
114 #define RT305X_ESW_POC0_DIS_PORT_S 23
115
116 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
117 #define RT305X_ESW_POC2_UNTAG_EN_S 0
118 #define RT305X_ESW_POC2_ENAGING_S 8
119 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
120
121 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
122 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
123 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
124 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
125
126 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
127 #define RT305X_ESW_PFC1_EN_VLAN_S 16
128 #define RT305X_ESW_PFC1_EN_TOS_S 24
129
130 #define RT305X_ESW_VLAN_NONE 0xfff
131
132 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
133 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
134
135 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
136 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
137
138 #define RT305X_ESW_POA_LINK_MASK 0x1f
139 #define RT305X_ESW_POA_LINK_SHIFT 25
140
141 #define RT305X_ESW_PORT_ST_CHG BIT(26)
142 #define RT305X_ESW_PORT0 0
143 #define RT305X_ESW_PORT1 1
144 #define RT305X_ESW_PORT2 2
145 #define RT305X_ESW_PORT3 3
146 #define RT305X_ESW_PORT4 4
147 #define RT305X_ESW_PORT5 5
148 #define RT305X_ESW_PORT6 6
149
150 #define RT305X_ESW_PORTS_NONE 0
151
152 #define RT305X_ESW_PMAP_LLLLLL 0x3f
153 #define RT305X_ESW_PMAP_LLLLWL 0x2f
154 #define RT305X_ESW_PMAP_WLLLLL 0x3e
155
156 #define RT305X_ESW_PORTS_INTERNAL \
157 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
158 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
159 BIT(RT305X_ESW_PORT4))
160
161 #define RT305X_ESW_PORTS_NOCPU \
162 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
163
164 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
165
166 #define RT305X_ESW_PORTS_ALL \
167 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
168
169 #define RT305X_ESW_NUM_VLANS 16
170 #define RT305X_ESW_NUM_VIDS 4096
171 #define RT305X_ESW_NUM_PORTS 7
172 #define RT305X_ESW_NUM_LANWAN 6
173 #define RT305X_ESW_NUM_LEDS 5
174
175 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
176 #define RT5350_EWS_REG_LED_POLARITY 0x168
177
178 enum {
179 /* Global attributes. */
180 RT305X_ESW_ATTR_ENABLE_VLAN,
181 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
182 RT305X_ESW_ATTR_BC_STATUS,
183 RT305X_ESW_ATTR_LED_FREQ,
184 /* Port attributes. */
185 RT305X_ESW_ATTR_PORT_DISABLE,
186 RT305X_ESW_ATTR_PORT_DOUBLETAG,
187 RT305X_ESW_ATTR_PORT_UNTAG,
188 RT305X_ESW_ATTR_PORT_LED,
189 RT305X_ESW_ATTR_PORT_LAN,
190 RT305X_ESW_ATTR_PORT_RECV_BAD,
191 RT305X_ESW_ATTR_PORT_RECV_GOOD,
192 RT5350_ESW_ATTR_PORT_TR_BAD,
193 RT5350_ESW_ATTR_PORT_TR_GOOD,
194 };
195
196 struct esw_port {
197 bool disable;
198 bool doubletag;
199 bool untag;
200 u8 led;
201 u16 pvid;
202 };
203
204 struct esw_vlan {
205 u8 ports;
206 u16 vid;
207 };
208
209 enum {
210 RT305X_ESW_VLAN_CONFIG_NONE = 0,
211 RT305X_ESW_VLAN_CONFIG_LLLLW,
212 RT305X_ESW_VLAN_CONFIG_WLLLL,
213 };
214
215 struct rt305x_esw {
216 struct device *dev;
217 void __iomem *base;
218 int irq;
219
220 /* Protects against concurrent register r/w operations. */
221 spinlock_t reg_rw_lock;
222
223 unsigned char port_map;
224 unsigned char port_disable;
225 unsigned int reg_initval_fct2;
226 unsigned int reg_initval_fpa2;
227 unsigned int reg_led_polarity;
228
229 struct switch_dev swdev;
230 bool global_vlan_enable;
231 bool alt_vlan_disable;
232 int bc_storm_protect;
233 int led_frequency;
234 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
235 struct esw_port ports[RT305X_ESW_NUM_PORTS];
236 struct reset_control *rst_esw;
237 struct reset_control *rst_ephy;
238
239 };
240
241 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
242 {
243 __raw_writel(val, esw->base + reg);
244 }
245
246 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
247 {
248 return __raw_readl(esw->base + reg);
249 }
250
251 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
252 unsigned long mask, unsigned long val)
253 {
254 unsigned long t;
255
256 t = __raw_readl(esw->base + reg) & ~mask;
257 __raw_writel(t | val, esw->base + reg);
258 }
259
260 static void esw_reset(struct rt305x_esw *esw)
261 {
262 if (!esw->rst_esw)
263 return;
264
265 reset_control_assert(esw->rst_esw);
266 usleep_range(60, 120);
267 reset_control_deassert(esw->rst_esw);
268 /* the esw takes long to reset otherwise the board hang */
269 msleep(10);
270 }
271
272 static void esw_reset_ephy(struct rt305x_esw *esw)
273 {
274 if (!esw->rst_ephy)
275 return;
276
277 reset_control_assert(esw->rst_ephy);
278 usleep_range(60, 120);
279 reset_control_deassert(esw->rst_ephy);
280 usleep_range(60, 120);
281 }
282
283 static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
284 unsigned long mask, unsigned long val)
285 {
286 unsigned long flags;
287
288 spin_lock_irqsave(&esw->reg_rw_lock, flags);
289 esw_rmw_raw(esw, reg, mask, val);
290 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
291 }
292
293 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
294 u32 phy_register, u32 write_data)
295 {
296 unsigned long t_start = jiffies;
297 int ret = 0;
298
299 while (1) {
300 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
301 RT305X_ESW_PCR1_WT_DONE))
302 break;
303 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
304 ret = 1;
305 goto out;
306 }
307 }
308
309 write_data &= 0xffff;
310 esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
311 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
312 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
313 RT305X_ESW_REG_PCR0);
314
315 t_start = jiffies;
316 while (1) {
317 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
318 RT305X_ESW_PCR1_WT_DONE)
319 break;
320
321 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
322 ret = 1;
323 break;
324 }
325 }
326 out:
327 if (ret)
328 dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
329 return ret;
330 }
331
332 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
333 {
334 unsigned s;
335 unsigned val;
336
337 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
338 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
339 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
340
341 return val;
342 }
343
344 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
345 {
346 unsigned s;
347
348 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
349 esw_rmw(esw,
350 RT305X_ESW_REG_VLANI(vlan / 2),
351 RT305X_ESW_VLANI_VID_M << s,
352 (vid & RT305X_ESW_VLANI_VID_M) << s);
353 }
354
355 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
356 {
357 unsigned s, val;
358
359 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
360 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
361 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
362 }
363
364 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
365 {
366 unsigned s;
367
368 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
369 esw_rmw(esw,
370 RT305X_ESW_REG_PVIDC(port / 2),
371 RT305X_ESW_PVIDC_PVID_M << s,
372 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
373 }
374
375 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
376 {
377 unsigned s, val;
378
379 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
380 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
381 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
382
383 return val;
384 }
385
386 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
387 {
388 unsigned s;
389
390 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
391 esw_rmw(esw,
392 RT305X_ESW_REG_VMSC(vlan / 4),
393 RT305X_ESW_VMSC_MSC_M << s,
394 (msc & RT305X_ESW_VMSC_MSC_M) << s);
395 }
396
397 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
398 {
399 unsigned reg;
400
401 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
402 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
403 RT305X_ESW_POC0_DIS_PORT_M;
404 }
405
406 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
407 {
408 unsigned old_mask;
409 unsigned enable_mask;
410 unsigned changed;
411 int i;
412
413 old_mask = esw_get_port_disable(esw);
414 changed = old_mask ^ disable_mask;
415 enable_mask = old_mask & disable_mask;
416
417 /* enable before writing to MII */
418 esw_rmw(esw, RT305X_ESW_REG_POC0,
419 (RT305X_ESW_POC0_DIS_PORT_M <<
420 RT305X_ESW_POC0_DIS_PORT_S),
421 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
422
423 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
424 if (!(changed & (1 << i)))
425 continue;
426 if (disable_mask & (1 << i)) {
427 /* disable */
428 rt305x_mii_write(esw, i, MII_BMCR,
429 BMCR_PDOWN);
430 } else {
431 /* enable */
432 rt305x_mii_write(esw, i, MII_BMCR,
433 BMCR_FULLDPLX |
434 BMCR_ANENABLE |
435 BMCR_ANRESTART |
436 BMCR_SPEED100);
437 }
438 }
439
440 /* disable after writing to MII */
441 esw_rmw(esw, RT305X_ESW_REG_POC0,
442 (RT305X_ESW_POC0_DIS_PORT_M <<
443 RT305X_ESW_POC0_DIS_PORT_S),
444 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
445 }
446
447 static void esw_set_gsc(struct rt305x_esw *esw)
448 {
449 esw_rmw(esw, RT305X_ESW_REG_SGC,
450 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
451 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
452 esw_rmw(esw, RT305X_ESW_REG_SGC,
453 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
454 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
455 }
456
457 static int esw_apply_config(struct switch_dev *dev);
458
459 static void esw_hw_init(struct rt305x_esw *esw)
460 {
461 int i;
462 u8 port_disable = 0;
463 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
464
465 /* vodoo from original driver */
466 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
467 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
468 /* Port priority 1 for all ports, vlan enabled. */
469 esw_w32(esw, 0x00005555 |
470 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
471 RT305X_ESW_REG_PFC1);
472
473 /* Enable all ports, Back Pressure and Flow Control */
474 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
475 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
476 RT305X_ESW_REG_POC0);
477
478 /* Enable Aging, and VLAN TAG removal */
479 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
480 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
481 RT305X_ESW_REG_POC2);
482
483 if (esw->reg_initval_fct2)
484 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
485 else
486 esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
487
488 /* 300s aging timer, max packet len 1536, broadcast storm prevention
489 * disabled, disable collision abort, mac xor48 hash, 10 packet back
490 * pressure jam, GMII disable was_transmit, back pressure disabled,
491 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
492 * ports.
493 */
494 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
495
496 /* Setup SoC Port control register */
497 esw_w32(esw,
498 (RT305X_ESW_SOCPC_CRC_PADDING |
499 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
500 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
501 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
502 RT305X_ESW_REG_SOCPC);
503
504 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
505 * turbo mii off, rgmi 3.3v off
506 * port5: disabled
507 * port6: enabled, gige, full-duplex, rx/tx-flow-control
508 */
509 if (esw->reg_initval_fpa2)
510 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
511 else
512 esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
513 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
514
515 /* Force Link/Activity on ports */
516 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
517 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
518 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
519 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
520 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
521
522 /* Copy disabled port configuration from device tree setup */
523 port_disable = esw->port_disable;
524
525 /* Disable nonexistent ports by reading the switch config
526 * after having enabled all possible ports above
527 */
528 port_disable |= esw_get_port_disable(esw);
529
530 for (i = 0; i < 6; i++)
531 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
532
533 if (ralink_soc == RT305X_SOC_RT3352) {
534 esw_reset_ephy(esw);
535
536 rt305x_mii_write(esw, 0, 31, 0x8000);
537 for (i = 0; i < 5; i++) {
538 if (esw->ports[i].disable) {
539 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
540 } else {
541 rt305x_mii_write(esw, i, MII_BMCR,
542 BMCR_FULLDPLX |
543 BMCR_ANENABLE |
544 BMCR_SPEED100);
545 }
546 /* TX10 waveform coefficient LSB=0 disable PHY */
547 rt305x_mii_write(esw, i, 26, 0x1601);
548 /* TX100/TX10 AD/DA current bias */
549 rt305x_mii_write(esw, i, 29, 0x7016);
550 /* TX100 slew rate control */
551 rt305x_mii_write(esw, i, 30, 0x0038);
552 }
553
554 /* select global register */
555 rt305x_mii_write(esw, 0, 31, 0x0);
556 /* enlarge agcsel threshold 3 and threshold 2 */
557 rt305x_mii_write(esw, 0, 1, 0x4a40);
558 /* enlarge agcsel threshold 5 and threshold 4 */
559 rt305x_mii_write(esw, 0, 2, 0x6254);
560 /* enlarge agcsel threshold */
561 rt305x_mii_write(esw, 0, 3, 0xa17f);
562 rt305x_mii_write(esw, 0, 12, 0x7eaa);
563 /* longer TP_IDL tail length */
564 rt305x_mii_write(esw, 0, 14, 0x65);
565 /* increased squelch pulse count threshold. */
566 rt305x_mii_write(esw, 0, 16, 0x0684);
567 /* set TX10 signal amplitude threshold to minimum */
568 rt305x_mii_write(esw, 0, 17, 0x0fe0);
569 /* set squelch amplitude to higher threshold */
570 rt305x_mii_write(esw, 0, 18, 0x40ba);
571 /* tune TP_IDL tail and head waveform, enable power
572 * down slew rate control
573 */
574 rt305x_mii_write(esw, 0, 22, 0x253f);
575 /* set PLL/Receive bias current are calibrated */
576 rt305x_mii_write(esw, 0, 27, 0x2fda);
577 /* change PLL/Receive bias current to internal(RT3350) */
578 rt305x_mii_write(esw, 0, 28, 0xc410);
579 /* change PLL bias current to internal(RT3052_MP3) */
580 rt305x_mii_write(esw, 0, 29, 0x598b);
581 /* select local register */
582 rt305x_mii_write(esw, 0, 31, 0x8000);
583 } else if (ralink_soc == RT305X_SOC_RT5350) {
584 esw_reset_ephy(esw);
585
586 /* set the led polarity */
587 esw_w32(esw, esw->reg_led_polarity & 0x1F,
588 RT5350_EWS_REG_LED_POLARITY);
589
590 /* local registers */
591 rt305x_mii_write(esw, 0, 31, 0x8000);
592 for (i = 0; i < 5; i++) {
593 if (esw->ports[i].disable) {
594 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
595 } else {
596 rt305x_mii_write(esw, i, MII_BMCR,
597 BMCR_FULLDPLX |
598 BMCR_ANENABLE |
599 BMCR_SPEED100);
600 }
601 /* TX10 waveform coefficient LSB=0 disable PHY */
602 rt305x_mii_write(esw, i, 26, 0x1601);
603 /* TX100/TX10 AD/DA current bias */
604 rt305x_mii_write(esw, i, 29, 0x7015);
605 /* TX100 slew rate control */
606 rt305x_mii_write(esw, i, 30, 0x0038);
607 }
608
609 /* global registers */
610 rt305x_mii_write(esw, 0, 31, 0x0);
611 /* enlarge agcsel threshold 3 and threshold 2 */
612 rt305x_mii_write(esw, 0, 1, 0x4a40);
613 /* enlarge agcsel threshold 5 and threshold 4 */
614 rt305x_mii_write(esw, 0, 2, 0x6254);
615 /* enlarge agcsel threshold 6 */
616 rt305x_mii_write(esw, 0, 3, 0xa17f);
617 rt305x_mii_write(esw, 0, 12, 0x7eaa);
618 /* longer TP_IDL tail length */
619 rt305x_mii_write(esw, 0, 14, 0x65);
620 /* increased squelch pulse count threshold. */
621 rt305x_mii_write(esw, 0, 16, 0x0684);
622 /* set TX10 signal amplitude threshold to minimum */
623 rt305x_mii_write(esw, 0, 17, 0x0fe0);
624 /* set squelch amplitude to higher threshold */
625 rt305x_mii_write(esw, 0, 18, 0x40ba);
626 /* tune TP_IDL tail and head waveform, enable power
627 * down slew rate control
628 */
629 rt305x_mii_write(esw, 0, 22, 0x253f);
630 /* set PLL/Receive bias current are calibrated */
631 rt305x_mii_write(esw, 0, 27, 0x2fda);
632 /* change PLL/Receive bias current to internal(RT3350) */
633 rt305x_mii_write(esw, 0, 28, 0xc410);
634 /* change PLL bias current to internal(RT3052_MP3) */
635 rt305x_mii_write(esw, 0, 29, 0x598b);
636 /* select local register */
637 rt305x_mii_write(esw, 0, 31, 0x8000);
638 } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
639 int i;
640
641 esw_reset_ephy(esw);
642
643 /* set the led polarity */
644 esw_w32(esw, esw->reg_led_polarity & 0x1F,
645 RT5350_EWS_REG_LED_POLARITY);
646
647 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
648 rt305x_mii_write(esw, 0, 26, 0x0020);
649
650 for (i = 0; i < 5; i++) {
651 rt305x_mii_write(esw, i, 31, 0x8000);
652 rt305x_mii_write(esw, i, 0, 0x3100);
653 rt305x_mii_write(esw, i, 30, 0xa000);
654 rt305x_mii_write(esw, i, 31, 0xa000);
655 rt305x_mii_write(esw, i, 16, 0x0606);
656 rt305x_mii_write(esw, i, 23, 0x0f0e);
657 rt305x_mii_write(esw, i, 24, 0x1610);
658 rt305x_mii_write(esw, i, 30, 0x1f15);
659 rt305x_mii_write(esw, i, 28, 0x6111);
660 rt305x_mii_write(esw, i, 31, 0x2000);
661 rt305x_mii_write(esw, i, 26, 0x0000);
662 }
663
664 /* 100Base AOI setting */
665 rt305x_mii_write(esw, 0, 31, 0x5000);
666 rt305x_mii_write(esw, 0, 19, 0x004a);
667 rt305x_mii_write(esw, 0, 20, 0x015a);
668 rt305x_mii_write(esw, 0, 21, 0x00ee);
669 rt305x_mii_write(esw, 0, 22, 0x0033);
670 rt305x_mii_write(esw, 0, 23, 0x020a);
671 rt305x_mii_write(esw, 0, 24, 0x0000);
672 rt305x_mii_write(esw, 0, 25, 0x024a);
673 rt305x_mii_write(esw, 0, 26, 0x035a);
674 rt305x_mii_write(esw, 0, 27, 0x02ee);
675 rt305x_mii_write(esw, 0, 28, 0x0233);
676 rt305x_mii_write(esw, 0, 29, 0x000a);
677 rt305x_mii_write(esw, 0, 30, 0x0000);
678 } else {
679 rt305x_mii_write(esw, 0, 31, 0x8000);
680 for (i = 0; i < 5; i++) {
681 if (esw->ports[i].disable) {
682 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
683 } else {
684 rt305x_mii_write(esw, i, MII_BMCR,
685 BMCR_FULLDPLX |
686 BMCR_ANENABLE |
687 BMCR_SPEED100);
688 }
689 /* TX10 waveform coefficient */
690 rt305x_mii_write(esw, i, 26, 0x1601);
691 /* TX100/TX10 AD/DA current bias */
692 rt305x_mii_write(esw, i, 29, 0x7058);
693 /* TX100 slew rate control */
694 rt305x_mii_write(esw, i, 30, 0x0018);
695 }
696
697 /* PHY IOT */
698 /* select global register */
699 rt305x_mii_write(esw, 0, 31, 0x0);
700 /* tune TP_IDL tail and head waveform */
701 rt305x_mii_write(esw, 0, 22, 0x052f);
702 /* set TX10 signal amplitude threshold to minimum */
703 rt305x_mii_write(esw, 0, 17, 0x0fe0);
704 /* set squelch amplitude to higher threshold */
705 rt305x_mii_write(esw, 0, 18, 0x40ba);
706 /* longer TP_IDL tail length */
707 rt305x_mii_write(esw, 0, 14, 0x65);
708 /* select local register */
709 rt305x_mii_write(esw, 0, 31, 0x8000);
710 }
711
712 if (esw->port_map)
713 port_map = esw->port_map;
714 else
715 port_map = RT305X_ESW_PMAP_LLLLLL;
716
717 /* Unused HW feature, but still nice to be consistent here...
718 * This is also exported to userspace ('lan' attribute) so it's
719 * conveniently usable to decide which ports go into the wan vlan by
720 * default.
721 */
722 esw_rmw(esw, RT305X_ESW_REG_SGC2,
723 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
724 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
725
726 /* make the switch leds blink */
727 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
728 esw->ports[i].led = 0x05;
729
730 /* Apply the empty config. */
731 esw_apply_config(&esw->swdev);
732
733 /* Only unmask the port change interrupt */
734 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
735 }
736
737 static irqreturn_t esw_interrupt(int irq, void *_esw)
738 {
739 struct rt305x_esw *esw = (struct rt305x_esw *)_esw;
740 u32 status;
741
742 status = esw_r32(esw, RT305X_ESW_REG_ISR);
743 if (status & RT305X_ESW_PORT_ST_CHG) {
744 u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
745
746 link >>= RT305X_ESW_POA_LINK_SHIFT;
747 link &= RT305X_ESW_POA_LINK_MASK;
748 dev_info(esw->dev, "link changed 0x%02X\n", link);
749 }
750 esw_w32(esw, status, RT305X_ESW_REG_ISR);
751
752 return IRQ_HANDLED;
753 }
754
755 static int esw_apply_config(struct switch_dev *dev)
756 {
757 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
758 int i;
759 u8 disable = 0;
760 u8 doubletag = 0;
761 u8 en_vlan = 0;
762 u8 untag = 0;
763
764 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
765 u32 vid, vmsc;
766 if (esw->global_vlan_enable) {
767 vid = esw->vlans[i].vid;
768 vmsc = esw->vlans[i].ports;
769 } else {
770 vid = RT305X_ESW_VLAN_NONE;
771 vmsc = RT305X_ESW_PORTS_NONE;
772 }
773 esw_set_vlan_id(esw, i, vid);
774 esw_set_vmsc(esw, i, vmsc);
775 }
776
777 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
778 u32 pvid;
779 disable |= esw->ports[i].disable << i;
780 if (esw->global_vlan_enable) {
781 doubletag |= esw->ports[i].doubletag << i;
782 en_vlan |= 1 << i;
783 untag |= esw->ports[i].untag << i;
784 pvid = esw->ports[i].pvid;
785 } else {
786 int x = esw->alt_vlan_disable ? 0 : 1;
787 doubletag |= x << i;
788 en_vlan |= x << i;
789 untag |= x << i;
790 pvid = 0;
791 }
792 esw_set_pvid(esw, i, pvid);
793 if (i < RT305X_ESW_NUM_LEDS)
794 esw_w32(esw, esw->ports[i].led,
795 RT305X_ESW_REG_P0LED + 4*i);
796 }
797
798 esw_set_gsc(esw);
799 esw_set_port_disable(esw, disable);
800 esw_rmw(esw, RT305X_ESW_REG_SGC2,
801 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
802 RT305X_ESW_SGC2_DOUBLE_TAG_S),
803 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
804 esw_rmw(esw, RT305X_ESW_REG_PFC1,
805 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
806 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
807 esw_rmw(esw, RT305X_ESW_REG_POC2,
808 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
809 untag << RT305X_ESW_POC2_UNTAG_EN_S);
810
811 if (!esw->global_vlan_enable) {
812 /*
813 * Still need to put all ports into vlan 0 or they'll be
814 * isolated.
815 * NOTE: vlan 0 is special, no vlan tag is prepended
816 */
817 esw_set_vlan_id(esw, 0, 0);
818 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
819 }
820
821 return 0;
822 }
823
824 static int esw_reset_switch(struct switch_dev *dev)
825 {
826 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
827
828 esw->global_vlan_enable = 0;
829 memset(esw->ports, 0, sizeof(esw->ports));
830 memset(esw->vlans, 0, sizeof(esw->vlans));
831 esw_hw_init(esw);
832
833 return 0;
834 }
835
836 static int esw_get_vlan_enable(struct switch_dev *dev,
837 const struct switch_attr *attr,
838 struct switch_val *val)
839 {
840 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
841
842 val->value.i = esw->global_vlan_enable;
843
844 return 0;
845 }
846
847 static int esw_set_vlan_enable(struct switch_dev *dev,
848 const struct switch_attr *attr,
849 struct switch_val *val)
850 {
851 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
852
853 esw->global_vlan_enable = val->value.i != 0;
854
855 return 0;
856 }
857
858 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
859 const struct switch_attr *attr,
860 struct switch_val *val)
861 {
862 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
863
864 val->value.i = esw->alt_vlan_disable;
865
866 return 0;
867 }
868
869 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
870 const struct switch_attr *attr,
871 struct switch_val *val)
872 {
873 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
874
875 esw->alt_vlan_disable = val->value.i != 0;
876
877 return 0;
878 }
879
880 static int
881 rt305x_esw_set_bc_status(struct switch_dev *dev,
882 const struct switch_attr *attr,
883 struct switch_val *val)
884 {
885 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
886
887 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
888
889 return 0;
890 }
891
892 static int
893 rt305x_esw_get_bc_status(struct switch_dev *dev,
894 const struct switch_attr *attr,
895 struct switch_val *val)
896 {
897 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
898
899 val->value.i = esw->bc_storm_protect;
900
901 return 0;
902 }
903
904 static int
905 rt305x_esw_set_led_freq(struct switch_dev *dev,
906 const struct switch_attr *attr,
907 struct switch_val *val)
908 {
909 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
910
911 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
912
913 return 0;
914 }
915
916 static int
917 rt305x_esw_get_led_freq(struct switch_dev *dev,
918 const struct switch_attr *attr,
919 struct switch_val *val)
920 {
921 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
922
923 val->value.i = esw->led_frequency;
924
925 return 0;
926 }
927
928 static int esw_get_port_link(struct switch_dev *dev,
929 int port,
930 struct switch_port_link *link)
931 {
932 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
933 u32 speed, poa;
934
935 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
936 return -EINVAL;
937
938 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
939
940 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
941 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
942 if (port < RT305X_ESW_NUM_LEDS) {
943 speed = (poa >> RT305X_ESW_SPD_S) & 1;
944 } else {
945 if (port == RT305X_ESW_NUM_PORTS - 1)
946 poa >>= 1;
947 speed = (poa >> RT305X_ESW_SPD_S) & 3;
948 }
949 switch (speed) {
950 case 0:
951 link->speed = SWITCH_PORT_SPEED_10;
952 break;
953 case 1:
954 link->speed = SWITCH_PORT_SPEED_100;
955 break;
956 case 2:
957 case 3: /* forced gige speed can be 2 or 3 */
958 link->speed = SWITCH_PORT_SPEED_1000;
959 break;
960 default:
961 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
962 break;
963 }
964
965 return 0;
966 }
967
968 static int esw_get_port_bool(struct switch_dev *dev,
969 const struct switch_attr *attr,
970 struct switch_val *val)
971 {
972 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
973 int idx = val->port_vlan;
974 u32 x, reg, shift;
975
976 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
977 return -EINVAL;
978
979 switch (attr->id) {
980 case RT305X_ESW_ATTR_PORT_DISABLE:
981 reg = RT305X_ESW_REG_POC0;
982 shift = RT305X_ESW_POC0_DIS_PORT_S;
983 break;
984 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
985 reg = RT305X_ESW_REG_SGC2;
986 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
987 break;
988 case RT305X_ESW_ATTR_PORT_UNTAG:
989 reg = RT305X_ESW_REG_POC2;
990 shift = RT305X_ESW_POC2_UNTAG_EN_S;
991 break;
992 case RT305X_ESW_ATTR_PORT_LAN:
993 reg = RT305X_ESW_REG_SGC2;
994 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
995 if (idx >= RT305X_ESW_NUM_LANWAN)
996 return -EINVAL;
997 break;
998 default:
999 return -EINVAL;
1000 }
1001
1002 x = esw_r32(esw, reg);
1003 val->value.i = (x >> (idx + shift)) & 1;
1004
1005 return 0;
1006 }
1007
1008 static int esw_set_port_bool(struct switch_dev *dev,
1009 const struct switch_attr *attr,
1010 struct switch_val *val)
1011 {
1012 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1013 int idx = val->port_vlan;
1014
1015 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1016 val->value.i < 0 || val->value.i > 1)
1017 return -EINVAL;
1018
1019 switch (attr->id) {
1020 case RT305X_ESW_ATTR_PORT_DISABLE:
1021 esw->ports[idx].disable = val->value.i;
1022 break;
1023 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1024 esw->ports[idx].doubletag = val->value.i;
1025 break;
1026 case RT305X_ESW_ATTR_PORT_UNTAG:
1027 esw->ports[idx].untag = val->value.i;
1028 break;
1029 default:
1030 return -EINVAL;
1031 }
1032
1033 return 0;
1034 }
1035
1036 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1037 const struct switch_attr *attr,
1038 struct switch_val *val)
1039 {
1040 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1041 int idx = val->port_vlan;
1042 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1043 u32 reg;
1044
1045 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1046 return -EINVAL;
1047 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1048 val->value.i = (reg >> shift) & 0xffff;
1049
1050 return 0;
1051 }
1052
1053 static int
1054 esw_get_port_tr_badgood(struct switch_dev *dev,
1055 const struct switch_attr *attr,
1056 struct switch_val *val)
1057 {
1058 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1059
1060 int idx = val->port_vlan;
1061 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1062 u32 reg;
1063
1064 if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
1065 return -EINVAL;
1066
1067 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1068 return -EINVAL;
1069
1070 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1071 val->value.i = (reg >> shift) & 0xffff;
1072
1073 return 0;
1074 }
1075
1076 static int esw_get_port_led(struct switch_dev *dev,
1077 const struct switch_attr *attr,
1078 struct switch_val *val)
1079 {
1080 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1081 int idx = val->port_vlan;
1082
1083 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1084 idx >= RT305X_ESW_NUM_LEDS)
1085 return -EINVAL;
1086
1087 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1088
1089 return 0;
1090 }
1091
1092 static int esw_set_port_led(struct switch_dev *dev,
1093 const struct switch_attr *attr,
1094 struct switch_val *val)
1095 {
1096 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1097 int idx = val->port_vlan;
1098
1099 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1100 return -EINVAL;
1101
1102 esw->ports[idx].led = val->value.i;
1103
1104 return 0;
1105 }
1106
1107 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1108 {
1109 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1110
1111 if (port >= RT305X_ESW_NUM_PORTS)
1112 return -EINVAL;
1113
1114 *val = esw_get_pvid(esw, port);
1115
1116 return 0;
1117 }
1118
1119 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1120 {
1121 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1122
1123 if (port >= RT305X_ESW_NUM_PORTS)
1124 return -EINVAL;
1125
1126 esw->ports[port].pvid = val;
1127
1128 return 0;
1129 }
1130
1131 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1132 {
1133 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1134 u32 vmsc, poc2;
1135 int vlan_idx = -1;
1136 int i;
1137
1138 val->len = 0;
1139
1140 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1141 return -EINVAL;
1142
1143 /* valid vlan? */
1144 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1145 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1146 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1147 vlan_idx = i;
1148 break;
1149 }
1150 }
1151
1152 if (vlan_idx == -1)
1153 return -EINVAL;
1154
1155 vmsc = esw_get_vmsc(esw, vlan_idx);
1156 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1157
1158 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1159 struct switch_port *p;
1160 int port_mask = 1 << i;
1161
1162 if (!(vmsc & port_mask))
1163 continue;
1164
1165 p = &val->value.ports[val->len++];
1166 p->id = i;
1167 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1168 p->flags = 0;
1169 else
1170 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1171 }
1172
1173 return 0;
1174 }
1175
1176 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1177 {
1178 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1179 int ports;
1180 int vlan_idx = -1;
1181 int i;
1182
1183 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1184 val->len > RT305X_ESW_NUM_PORTS)
1185 return -EINVAL;
1186
1187 /* one of the already defined vlans? */
1188 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1189 if (esw->vlans[i].vid == val->port_vlan &&
1190 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1191 vlan_idx = i;
1192 break;
1193 }
1194 }
1195
1196 /* select a free slot */
1197 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1198 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1199 vlan_idx = i;
1200 }
1201
1202 /* bail if all slots are in use */
1203 if (vlan_idx == -1)
1204 return -EINVAL;
1205
1206 ports = RT305X_ESW_PORTS_NONE;
1207 for (i = 0; i < val->len; i++) {
1208 struct switch_port *p = &val->value.ports[i];
1209 int port_mask = 1 << p->id;
1210 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1211
1212 if (p->id >= RT305X_ESW_NUM_PORTS)
1213 return -EINVAL;
1214
1215 ports |= port_mask;
1216 esw->ports[p->id].untag = untagged;
1217 }
1218 esw->vlans[vlan_idx].ports = ports;
1219 if (ports == RT305X_ESW_PORTS_NONE)
1220 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1221 else
1222 esw->vlans[vlan_idx].vid = val->port_vlan;
1223
1224 return 0;
1225 }
1226
1227 static const struct switch_attr esw_global[] = {
1228 {
1229 .type = SWITCH_TYPE_INT,
1230 .name = "enable_vlan",
1231 .description = "VLAN mode (1:enabled)",
1232 .max = 1,
1233 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1234 .get = esw_get_vlan_enable,
1235 .set = esw_set_vlan_enable,
1236 },
1237 {
1238 .type = SWITCH_TYPE_INT,
1239 .name = "alternate_vlan_disable",
1240 .description = "Use en_vlan instead of doubletag to disable"
1241 " VLAN mode",
1242 .max = 1,
1243 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1244 .get = esw_get_alt_vlan_disable,
1245 .set = esw_set_alt_vlan_disable,
1246 },
1247 {
1248 .type = SWITCH_TYPE_INT,
1249 .name = "bc_storm_protect",
1250 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1251 .max = 3,
1252 .id = RT305X_ESW_ATTR_BC_STATUS,
1253 .get = rt305x_esw_get_bc_status,
1254 .set = rt305x_esw_set_bc_status,
1255 },
1256 {
1257 .type = SWITCH_TYPE_INT,
1258 .name = "led_frequency",
1259 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1260 .max = 3,
1261 .id = RT305X_ESW_ATTR_LED_FREQ,
1262 .get = rt305x_esw_get_led_freq,
1263 .set = rt305x_esw_set_led_freq,
1264 }
1265 };
1266
1267 static const struct switch_attr esw_port[] = {
1268 {
1269 .type = SWITCH_TYPE_INT,
1270 .name = "disable",
1271 .description = "Port state (1:disabled)",
1272 .max = 1,
1273 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1274 .get = esw_get_port_bool,
1275 .set = esw_set_port_bool,
1276 },
1277 {
1278 .type = SWITCH_TYPE_INT,
1279 .name = "doubletag",
1280 .description = "Double tagging for incoming vlan packets "
1281 "(1:enabled)",
1282 .max = 1,
1283 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1284 .get = esw_get_port_bool,
1285 .set = esw_set_port_bool,
1286 },
1287 {
1288 .type = SWITCH_TYPE_INT,
1289 .name = "untag",
1290 .description = "Untag (1:strip outgoing vlan tag)",
1291 .max = 1,
1292 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1293 .get = esw_get_port_bool,
1294 .set = esw_set_port_bool,
1295 },
1296 {
1297 .type = SWITCH_TYPE_INT,
1298 .name = "led",
1299 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1300 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1301 " 8:100mact, 10:blink, 11:off, 12:on)",
1302 .max = 15,
1303 .id = RT305X_ESW_ATTR_PORT_LED,
1304 .get = esw_get_port_led,
1305 .set = esw_set_port_led,
1306 },
1307 {
1308 .type = SWITCH_TYPE_INT,
1309 .name = "lan",
1310 .description = "HW port group (0:wan, 1:lan)",
1311 .max = 1,
1312 .id = RT305X_ESW_ATTR_PORT_LAN,
1313 .get = esw_get_port_bool,
1314 },
1315 {
1316 .type = SWITCH_TYPE_INT,
1317 .name = "recv_bad",
1318 .description = "Receive bad packet counter",
1319 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1320 .get = esw_get_port_recv_badgood,
1321 },
1322 {
1323 .type = SWITCH_TYPE_INT,
1324 .name = "recv_good",
1325 .description = "Receive good packet counter",
1326 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1327 .get = esw_get_port_recv_badgood,
1328 },
1329 {
1330 .type = SWITCH_TYPE_INT,
1331 .name = "tr_bad",
1332
1333 .description = "Transmit bad packet counter. rt5350 only",
1334 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1335 .get = esw_get_port_tr_badgood,
1336 },
1337 {
1338 .type = SWITCH_TYPE_INT,
1339 .name = "tr_good",
1340
1341 .description = "Transmit good packet counter. rt5350 only",
1342 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1343 .get = esw_get_port_tr_badgood,
1344 },
1345 };
1346
1347 static const struct switch_attr esw_vlan[] = {
1348 };
1349
1350 static const struct switch_dev_ops esw_ops = {
1351 .attr_global = {
1352 .attr = esw_global,
1353 .n_attr = ARRAY_SIZE(esw_global),
1354 },
1355 .attr_port = {
1356 .attr = esw_port,
1357 .n_attr = ARRAY_SIZE(esw_port),
1358 },
1359 .attr_vlan = {
1360 .attr = esw_vlan,
1361 .n_attr = ARRAY_SIZE(esw_vlan),
1362 },
1363 .get_vlan_ports = esw_get_vlan_ports,
1364 .set_vlan_ports = esw_set_vlan_ports,
1365 .get_port_pvid = esw_get_port_pvid,
1366 .set_port_pvid = esw_set_port_pvid,
1367 .get_port_link = esw_get_port_link,
1368 .apply_config = esw_apply_config,
1369 .reset_switch = esw_reset_switch,
1370 };
1371
1372 static int esw_probe(struct platform_device *pdev)
1373 {
1374 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1375 struct device_node *np = pdev->dev.of_node;
1376 const __be32 *port_map, *port_disable, *reg_init;
1377 struct switch_dev *swdev;
1378 struct rt305x_esw *esw;
1379 int ret;
1380
1381 esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
1382 if (!esw)
1383 return -ENOMEM;
1384
1385 esw->dev = &pdev->dev;
1386 esw->irq = irq_of_parse_and_map(np, 0);
1387 esw->base = devm_ioremap_resource(&pdev->dev, res);
1388 if (IS_ERR(esw->base))
1389 return PTR_ERR(esw->base);
1390
1391 port_map = of_get_property(np, "mediatek,portmap", NULL);
1392 if (port_map)
1393 esw->port_map = be32_to_cpu(*port_map);
1394
1395 port_disable = of_get_property(np, "mediatek,portdisable", NULL);
1396 if (port_disable)
1397 esw->port_disable = be32_to_cpu(*port_disable);
1398
1399 reg_init = of_get_property(np, "ralink,fct2", NULL);
1400 if (reg_init)
1401 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1402
1403 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1404 if (reg_init)
1405 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1406
1407 reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
1408 if (reg_init)
1409 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1410
1411 esw->rst_esw = devm_reset_control_get(&pdev->dev, "esw");
1412 if (IS_ERR(esw->rst_esw))
1413 esw->rst_esw = NULL;
1414 esw->rst_ephy = devm_reset_control_get(&pdev->dev, "ephy");
1415 if (IS_ERR(esw->rst_ephy))
1416 esw->rst_ephy = NULL;
1417
1418 swdev = &esw->swdev;
1419 swdev->of_node = pdev->dev.of_node;
1420 swdev->name = "rt305x-esw";
1421 swdev->alias = "rt305x";
1422 swdev->cpu_port = RT305X_ESW_PORT6;
1423 swdev->ports = RT305X_ESW_NUM_PORTS;
1424 swdev->vlans = RT305X_ESW_NUM_VIDS;
1425 swdev->ops = &esw_ops;
1426
1427 ret = register_switch(swdev, NULL);
1428 if (ret < 0) {
1429 dev_err(&pdev->dev, "register_switch failed\n");
1430 return ret;
1431 }
1432
1433 platform_set_drvdata(pdev, esw);
1434
1435 spin_lock_init(&esw->reg_rw_lock);
1436
1437 esw_hw_init(esw);
1438
1439 reg_init = of_get_property(np, "ralink,rgmii", NULL);
1440 if (reg_init && be32_to_cpu(*reg_init) == 1) {
1441 /*
1442 * External switch connected to RGMII interface.
1443 * Unregister the switch device after initialization.
1444 */
1445 dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
1446 unregister_switch(&esw->swdev);
1447 platform_set_drvdata(pdev, NULL);
1448 return -ENODEV;
1449 }
1450
1451 ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
1452 esw);
1453
1454 if (!ret) {
1455 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1456 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1457 }
1458
1459 return ret;
1460 }
1461
1462 static int esw_remove(struct platform_device *pdev)
1463 {
1464 struct rt305x_esw *esw = platform_get_drvdata(pdev);
1465
1466 if (esw) {
1467 esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
1468 platform_set_drvdata(pdev, NULL);
1469 }
1470
1471 return 0;
1472 }
1473
1474 static const struct of_device_id ralink_esw_match[] = {
1475 { .compatible = "ralink,rt3050-esw" },
1476 {},
1477 };
1478 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1479
1480 static struct platform_driver esw_driver = {
1481 .probe = esw_probe,
1482 .remove = esw_remove,
1483 .driver = {
1484 .name = "rt3050-esw",
1485 .owner = THIS_MODULE,
1486 .of_match_table = ralink_esw_match,
1487 },
1488 };
1489
1490 module_platform_driver(esw_driver);
1491
1492 MODULE_LICENSE("GPL");
1493 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1494 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1495 MODULE_VERSION(MTK_FE_DRV_VERSION);
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