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ramips: ethernet: ralink: add led_source dts-binding
[openwrt/staging/jow.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3050.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22
23 #include <linux/switch.h>
24 #include <linux/reset.h>
25
26 #include "mtk_eth_soc.h"
27 #include "esw_rt3050.h"
28
29 /* HW limitations for this switch:
30 * - No large frame support (PKT_MAX_LEN at most 1536)
31 * - Can't have untagged vlan and tagged vlan on one port at the same time,
32 * though this might be possible using the undocumented PPE.
33 */
34
35 #define RT305X_ESW_REG_ISR 0x00
36 #define RT305X_ESW_REG_IMR 0x04
37 #define RT305X_ESW_REG_FCT0 0x08
38 #define RT305X_ESW_REG_PFC1 0x14
39 #define RT305X_ESW_REG_ATS 0x24
40 #define RT305X_ESW_REG_ATS0 0x28
41 #define RT305X_ESW_REG_ATS1 0x2c
42 #define RT305X_ESW_REG_ATS2 0x30
43 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
44 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
45 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
46 #define RT305X_ESW_REG_POA 0x80
47 #define RT305X_ESW_REG_FPA 0x84
48 #define RT305X_ESW_REG_SOCPC 0x8c
49 #define RT305X_ESW_REG_POC0 0x90
50 #define RT305X_ESW_REG_POC1 0x94
51 #define RT305X_ESW_REG_POC2 0x98
52 #define RT305X_ESW_REG_SGC 0x9c
53 #define RT305X_ESW_REG_STRT 0xa0
54 #define RT305X_ESW_REG_PCR0 0xc0
55 #define RT305X_ESW_REG_PCR1 0xc4
56 #define RT305X_ESW_REG_FPA2 0xc8
57 #define RT305X_ESW_REG_FCT2 0xcc
58 #define RT305X_ESW_REG_SGC2 0xe4
59 #define RT305X_ESW_REG_P0LED 0xa4
60 #define RT305X_ESW_REG_P1LED 0xa8
61 #define RT305X_ESW_REG_P2LED 0xac
62 #define RT305X_ESW_REG_P3LED 0xb0
63 #define RT305X_ESW_REG_P4LED 0xb4
64 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
65 #define RT305X_ESW_REG_P1PC 0xec
66 #define RT305X_ESW_REG_P2PC 0xf0
67 #define RT305X_ESW_REG_P3PC 0xf4
68 #define RT305X_ESW_REG_P4PC 0xf8
69 #define RT305X_ESW_REG_P5PC 0xfc
70
71 #define RT305X_ESW_LED_LINK 0
72 #define RT305X_ESW_LED_100M 1
73 #define RT305X_ESW_LED_DUPLEX 2
74 #define RT305X_ESW_LED_ACTIVITY 3
75 #define RT305X_ESW_LED_COLLISION 4
76 #define RT305X_ESW_LED_LINKACT 5
77 #define RT305X_ESW_LED_DUPLCOLL 6
78 #define RT305X_ESW_LED_10MACT 7
79 #define RT305X_ESW_LED_100MACT 8
80 /* Additional led states not in datasheet: */
81 #define RT305X_ESW_LED_BLINK 10
82 #define RT305X_ESW_LED_OFF 11
83 #define RT305X_ESW_LED_ON 12
84
85 #define RT305X_ESW_LINK_S 25
86 #define RT305X_ESW_DUPLEX_S 9
87 #define RT305X_ESW_SPD_S 0
88
89 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
90 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
91 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
92
93 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
94
95 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
96 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
97
98 #define RT305X_ESW_PVIDC_PVID_M 0xfff
99 #define RT305X_ESW_PVIDC_PVID_S 12
100
101 #define RT305X_ESW_VLANI_VID_M 0xfff
102 #define RT305X_ESW_VLANI_VID_S 12
103
104 #define RT305X_ESW_VMSC_MSC_M 0xff
105 #define RT305X_ESW_VMSC_MSC_S 8
106
107 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
108 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
109 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
110 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
111
112 #define RT305X_ESW_POC0_EN_BP_S 0
113 #define RT305X_ESW_POC0_EN_FC_S 8
114 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
115 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
116 #define RT305X_ESW_POC0_DIS_PORT_S 23
117
118 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
119 #define RT305X_ESW_POC2_UNTAG_EN_S 0
120 #define RT305X_ESW_POC2_ENAGING_S 8
121 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
122
123 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
124 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
125 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
126 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
127
128 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
129 #define RT305X_ESW_PFC1_EN_VLAN_S 16
130 #define RT305X_ESW_PFC1_EN_TOS_S 24
131
132 #define RT305X_ESW_VLAN_NONE 0xfff
133
134 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
135 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
136
137 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
138 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
139
140 #define RT305X_ESW_POA_LINK_MASK 0x1f
141 #define RT305X_ESW_POA_LINK_SHIFT 25
142
143 #define RT305X_ESW_PORT_ST_CHG BIT(26)
144 #define RT305X_ESW_PORT0 0
145 #define RT305X_ESW_PORT1 1
146 #define RT305X_ESW_PORT2 2
147 #define RT305X_ESW_PORT3 3
148 #define RT305X_ESW_PORT4 4
149 #define RT305X_ESW_PORT5 5
150 #define RT305X_ESW_PORT6 6
151
152 #define RT305X_ESW_PORTS_NONE 0
153
154 #define RT305X_ESW_PMAP_LLLLLL 0x3f
155 #define RT305X_ESW_PMAP_LLLLWL 0x2f
156 #define RT305X_ESW_PMAP_WLLLLL 0x3e
157
158 #define RT305X_ESW_PORTS_INTERNAL \
159 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
160 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
161 BIT(RT305X_ESW_PORT4))
162
163 #define RT305X_ESW_PORTS_NOCPU \
164 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
165
166 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
167
168 #define RT305X_ESW_PORTS_ALL \
169 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
170
171 #define RT305X_ESW_NUM_VLANS 16
172 #define RT305X_ESW_NUM_VIDS 4096
173 #define RT305X_ESW_NUM_PORTS 7
174 #define RT305X_ESW_NUM_LANWAN 6
175 #define RT305X_ESW_NUM_LEDS 5
176
177 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
178 #define RT5350_EWS_REG_LED_CONTROL 0x168
179
180 enum {
181 /* Global attributes. */
182 RT305X_ESW_ATTR_ENABLE_VLAN,
183 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
184 RT305X_ESW_ATTR_BC_STATUS,
185 RT305X_ESW_ATTR_LED_FREQ,
186 /* Port attributes. */
187 RT305X_ESW_ATTR_PORT_DISABLE,
188 RT305X_ESW_ATTR_PORT_DOUBLETAG,
189 RT305X_ESW_ATTR_PORT_UNTAG,
190 RT305X_ESW_ATTR_PORT_LED,
191 RT305X_ESW_ATTR_PORT_LAN,
192 RT305X_ESW_ATTR_PORT_RECV_BAD,
193 RT305X_ESW_ATTR_PORT_RECV_GOOD,
194 RT5350_ESW_ATTR_PORT_TR_BAD,
195 RT5350_ESW_ATTR_PORT_TR_GOOD,
196 };
197
198 struct esw_port {
199 bool disable;
200 bool doubletag;
201 bool untag;
202 u8 led;
203 u16 pvid;
204 };
205
206 struct esw_vlan {
207 u8 ports;
208 u16 vid;
209 };
210
211 enum {
212 RT305X_ESW_VLAN_CONFIG_NONE = 0,
213 RT305X_ESW_VLAN_CONFIG_LLLLW,
214 RT305X_ESW_VLAN_CONFIG_WLLLL,
215 };
216
217 struct rt305x_esw {
218 struct device *dev;
219 void __iomem *base;
220 int irq;
221 struct fe_priv *priv;
222
223 /* Protects against concurrent register r/w operations. */
224 spinlock_t reg_rw_lock;
225
226 unsigned char port_map;
227 unsigned char port_disable;
228 unsigned int reg_initval_fct2;
229 unsigned int reg_initval_fpa2;
230 unsigned int reg_led_polarity;
231 unsigned int reg_led_source;
232
233 struct switch_dev swdev;
234 bool global_vlan_enable;
235 bool alt_vlan_disable;
236 int bc_storm_protect;
237 int led_frequency;
238 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
239 struct esw_port ports[RT305X_ESW_NUM_PORTS];
240 struct reset_control *rst_esw;
241 struct reset_control *rst_ephy;
242
243 };
244
245 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
246 {
247 __raw_writel(val, esw->base + reg);
248 }
249
250 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
251 {
252 return __raw_readl(esw->base + reg);
253 }
254
255 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
256 unsigned long mask, unsigned long val)
257 {
258 unsigned long t;
259
260 t = __raw_readl(esw->base + reg) & ~mask;
261 __raw_writel(t | val, esw->base + reg);
262 }
263
264 static void esw_reset(struct rt305x_esw *esw)
265 {
266 if (!esw->rst_esw)
267 return;
268
269 reset_control_assert(esw->rst_esw);
270 usleep_range(60, 120);
271 reset_control_deassert(esw->rst_esw);
272 /* the esw takes long to reset otherwise the board hang */
273 msleep(10);
274 }
275
276 static void esw_reset_ephy(struct rt305x_esw *esw)
277 {
278 if (!esw->rst_ephy)
279 return;
280
281 reset_control_assert(esw->rst_ephy);
282 usleep_range(60, 120);
283 reset_control_deassert(esw->rst_ephy);
284 usleep_range(60, 120);
285 }
286
287 static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
288 unsigned long mask, unsigned long val)
289 {
290 unsigned long flags;
291
292 spin_lock_irqsave(&esw->reg_rw_lock, flags);
293 esw_rmw_raw(esw, reg, mask, val);
294 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
295 }
296
297 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
298 u32 phy_register, u32 write_data)
299 {
300 unsigned long t_start = jiffies;
301 int ret = 0;
302
303 while (1) {
304 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
305 RT305X_ESW_PCR1_WT_DONE))
306 break;
307 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
308 ret = 1;
309 goto out;
310 }
311 }
312
313 write_data &= 0xffff;
314 esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
315 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
316 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
317 RT305X_ESW_REG_PCR0);
318
319 t_start = jiffies;
320 while (1) {
321 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
322 RT305X_ESW_PCR1_WT_DONE)
323 break;
324
325 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
326 ret = 1;
327 break;
328 }
329 }
330 out:
331 if (ret)
332 dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
333 return ret;
334 }
335
336 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
337 {
338 unsigned s;
339 unsigned val;
340
341 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
342 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
343 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
344
345 return val;
346 }
347
348 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
349 {
350 unsigned s;
351
352 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
353 esw_rmw(esw,
354 RT305X_ESW_REG_VLANI(vlan / 2),
355 RT305X_ESW_VLANI_VID_M << s,
356 (vid & RT305X_ESW_VLANI_VID_M) << s);
357 }
358
359 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
360 {
361 unsigned s, val;
362
363 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
364 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
365 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
366 }
367
368 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
369 {
370 unsigned s;
371
372 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
373 esw_rmw(esw,
374 RT305X_ESW_REG_PVIDC(port / 2),
375 RT305X_ESW_PVIDC_PVID_M << s,
376 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
377 }
378
379 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
380 {
381 unsigned s, val;
382
383 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
384 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
385 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
386
387 return val;
388 }
389
390 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
391 {
392 unsigned s;
393
394 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
395 esw_rmw(esw,
396 RT305X_ESW_REG_VMSC(vlan / 4),
397 RT305X_ESW_VMSC_MSC_M << s,
398 (msc & RT305X_ESW_VMSC_MSC_M) << s);
399 }
400
401 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
402 {
403 unsigned reg;
404
405 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
406 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
407 RT305X_ESW_POC0_DIS_PORT_M;
408 }
409
410 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
411 {
412 unsigned old_mask;
413 unsigned enable_mask;
414 unsigned changed;
415 int i;
416
417 old_mask = esw_get_port_disable(esw);
418 changed = old_mask ^ disable_mask;
419 enable_mask = old_mask & disable_mask;
420
421 /* enable before writing to MII */
422 esw_rmw(esw, RT305X_ESW_REG_POC0,
423 (RT305X_ESW_POC0_DIS_PORT_M <<
424 RT305X_ESW_POC0_DIS_PORT_S),
425 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
426
427 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
428 if (!(changed & (1 << i)))
429 continue;
430 if (disable_mask & (1 << i)) {
431 /* disable */
432 rt305x_mii_write(esw, i, MII_BMCR,
433 BMCR_PDOWN);
434 } else {
435 /* enable */
436 rt305x_mii_write(esw, i, MII_BMCR,
437 BMCR_FULLDPLX |
438 BMCR_ANENABLE |
439 BMCR_ANRESTART |
440 BMCR_SPEED100);
441 }
442 }
443
444 /* disable after writing to MII */
445 esw_rmw(esw, RT305X_ESW_REG_POC0,
446 (RT305X_ESW_POC0_DIS_PORT_M <<
447 RT305X_ESW_POC0_DIS_PORT_S),
448 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
449 }
450
451 static void esw_set_gsc(struct rt305x_esw *esw)
452 {
453 esw_rmw(esw, RT305X_ESW_REG_SGC,
454 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
455 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
456 esw_rmw(esw, RT305X_ESW_REG_SGC,
457 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
458 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
459 }
460
461 static int esw_apply_config(struct switch_dev *dev);
462
463 static void esw_hw_init(struct rt305x_esw *esw)
464 {
465 int i;
466 u8 port_disable = 0;
467 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
468
469 esw_reset(esw);
470
471 /* vodoo from original driver */
472 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
473 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
474 /* Port priority 1 for all ports, vlan enabled. */
475 esw_w32(esw, 0x00005555 |
476 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
477 RT305X_ESW_REG_PFC1);
478
479 /* Enable all ports, Back Pressure and Flow Control */
480 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
481 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
482 RT305X_ESW_REG_POC0);
483
484 /* Enable Aging, and VLAN TAG removal */
485 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
486 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
487 RT305X_ESW_REG_POC2);
488
489 if (esw->reg_initval_fct2)
490 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
491 else
492 esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
493
494 /* 300s aging timer, max packet len 1536, broadcast storm prevention
495 * disabled, disable collision abort, mac xor48 hash, 10 packet back
496 * pressure jam, GMII disable was_transmit, back pressure disabled,
497 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
498 * ports.
499 */
500 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
501
502 /* Setup SoC Port control register */
503 esw_w32(esw,
504 (RT305X_ESW_SOCPC_CRC_PADDING |
505 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
506 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
507 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
508 RT305X_ESW_REG_SOCPC);
509
510 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
511 * turbo mii off, rgmi 3.3v off
512 * port5: disabled
513 * port6: enabled, gige, full-duplex, rx/tx-flow-control
514 */
515 if (esw->reg_initval_fpa2)
516 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
517 else
518 esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
519 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
520
521 /* Force Link/Activity on ports */
522 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P0LED);
523 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P1LED);
524 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P2LED);
525 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P3LED);
526 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P4LED);
527
528 /* Copy disabled port configuration from device tree setup */
529 port_disable = esw->port_disable;
530
531 /* Disable nonexistent ports by reading the switch config
532 * after having enabled all possible ports above
533 */
534 port_disable |= esw_get_port_disable(esw);
535
536 for (i = 0; i < 6; i++)
537 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
538
539 if (ralink_soc == RT305X_SOC_RT3352) {
540 esw_reset_ephy(esw);
541
542 rt305x_mii_write(esw, 0, 31, 0x8000);
543 for (i = 0; i < 5; i++) {
544 if (esw->ports[i].disable) {
545 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
546 } else {
547 rt305x_mii_write(esw, i, MII_BMCR,
548 BMCR_FULLDPLX |
549 BMCR_ANENABLE |
550 BMCR_SPEED100);
551 }
552 /* TX10 waveform coefficient LSB=0 disable PHY */
553 rt305x_mii_write(esw, i, 26, 0x1601);
554 /* TX100/TX10 AD/DA current bias */
555 rt305x_mii_write(esw, i, 29, 0x7016);
556 /* TX100 slew rate control */
557 rt305x_mii_write(esw, i, 30, 0x0038);
558 }
559
560 /* select global register */
561 rt305x_mii_write(esw, 0, 31, 0x0);
562 /* enlarge agcsel threshold 3 and threshold 2 */
563 rt305x_mii_write(esw, 0, 1, 0x4a40);
564 /* enlarge agcsel threshold 5 and threshold 4 */
565 rt305x_mii_write(esw, 0, 2, 0x6254);
566 /* enlarge agcsel threshold */
567 rt305x_mii_write(esw, 0, 3, 0xa17f);
568 rt305x_mii_write(esw, 0, 12, 0x7eaa);
569 /* longer TP_IDL tail length */
570 rt305x_mii_write(esw, 0, 14, 0x65);
571 /* increased squelch pulse count threshold. */
572 rt305x_mii_write(esw, 0, 16, 0x0684);
573 /* set TX10 signal amplitude threshold to minimum */
574 rt305x_mii_write(esw, 0, 17, 0x0fe0);
575 /* set squelch amplitude to higher threshold */
576 rt305x_mii_write(esw, 0, 18, 0x40ba);
577 /* tune TP_IDL tail and head waveform, enable power
578 * down slew rate control
579 */
580 rt305x_mii_write(esw, 0, 22, 0x253f);
581 /* set PLL/Receive bias current are calibrated */
582 rt305x_mii_write(esw, 0, 27, 0x2fda);
583 /* change PLL/Receive bias current to internal(RT3350) */
584 rt305x_mii_write(esw, 0, 28, 0xc410);
585 /* change PLL bias current to internal(RT3052_MP3) */
586 rt305x_mii_write(esw, 0, 29, 0x598b);
587 /* select local register */
588 rt305x_mii_write(esw, 0, 31, 0x8000);
589 } else if (ralink_soc == RT305X_SOC_RT5350) {
590 esw_reset_ephy(esw);
591
592 /* set the led polarity */
593 esw_w32(esw, esw->reg_led_polarity & 0x1F,
594 RT5350_EWS_REG_LED_CONTROL);
595
596 /* local registers */
597 rt305x_mii_write(esw, 0, 31, 0x8000);
598 for (i = 0; i < 5; i++) {
599 if (esw->ports[i].disable) {
600 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
601 } else {
602 rt305x_mii_write(esw, i, MII_BMCR,
603 BMCR_FULLDPLX |
604 BMCR_ANENABLE |
605 BMCR_SPEED100);
606 }
607 /* TX10 waveform coefficient LSB=0 disable PHY */
608 rt305x_mii_write(esw, i, 26, 0x1601);
609 /* TX100/TX10 AD/DA current bias */
610 rt305x_mii_write(esw, i, 29, 0x7015);
611 /* TX100 slew rate control */
612 rt305x_mii_write(esw, i, 30, 0x0038);
613 }
614
615 /* global registers */
616 rt305x_mii_write(esw, 0, 31, 0x0);
617 /* enlarge agcsel threshold 3 and threshold 2 */
618 rt305x_mii_write(esw, 0, 1, 0x4a40);
619 /* enlarge agcsel threshold 5 and threshold 4 */
620 rt305x_mii_write(esw, 0, 2, 0x6254);
621 /* enlarge agcsel threshold 6 */
622 rt305x_mii_write(esw, 0, 3, 0xa17f);
623 rt305x_mii_write(esw, 0, 12, 0x7eaa);
624 /* longer TP_IDL tail length */
625 rt305x_mii_write(esw, 0, 14, 0x65);
626 /* increased squelch pulse count threshold. */
627 rt305x_mii_write(esw, 0, 16, 0x0684);
628 /* set TX10 signal amplitude threshold to minimum */
629 rt305x_mii_write(esw, 0, 17, 0x0fe0);
630 /* set squelch amplitude to higher threshold */
631 rt305x_mii_write(esw, 0, 18, 0x40ba);
632 /* tune TP_IDL tail and head waveform, enable power
633 * down slew rate control
634 */
635 rt305x_mii_write(esw, 0, 22, 0x253f);
636 /* set PLL/Receive bias current are calibrated */
637 rt305x_mii_write(esw, 0, 27, 0x2fda);
638 /* change PLL/Receive bias current to internal(RT3350) */
639 rt305x_mii_write(esw, 0, 28, 0xc410);
640 /* change PLL bias current to internal(RT3052_MP3) */
641 rt305x_mii_write(esw, 0, 29, 0x598b);
642 /* select local register */
643 rt305x_mii_write(esw, 0, 31, 0x8000);
644 } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
645 int i;
646
647 esw_reset_ephy(esw);
648
649 /* set the led polarity and led source */
650 esw_w32(esw, (esw->reg_led_polarity & 0x1F) |
651 ((esw->reg_led_source << 8) & 0x700),
652 RT5350_EWS_REG_LED_CONTROL);
653
654 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
655 rt305x_mii_write(esw, 0, 26, 0x0020);
656
657 for (i = 0; i < 5; i++) {
658 rt305x_mii_write(esw, i, 31, 0x8000);
659 rt305x_mii_write(esw, i, 0, 0x3100);
660 rt305x_mii_write(esw, i, 30, 0xa000);
661 rt305x_mii_write(esw, i, 31, 0xa000);
662 rt305x_mii_write(esw, i, 16, 0x0606);
663 rt305x_mii_write(esw, i, 23, 0x0f0e);
664 rt305x_mii_write(esw, i, 24, 0x1610);
665 rt305x_mii_write(esw, i, 30, 0x1f15);
666 rt305x_mii_write(esw, i, 28, 0x6111);
667 rt305x_mii_write(esw, i, 31, 0x2000);
668 rt305x_mii_write(esw, i, 26, 0x0000);
669 }
670
671 /* 100Base AOI setting */
672 rt305x_mii_write(esw, 0, 31, 0x5000);
673 rt305x_mii_write(esw, 0, 19, 0x004a);
674 rt305x_mii_write(esw, 0, 20, 0x015a);
675 rt305x_mii_write(esw, 0, 21, 0x00ee);
676 rt305x_mii_write(esw, 0, 22, 0x0033);
677 rt305x_mii_write(esw, 0, 23, 0x020a);
678 rt305x_mii_write(esw, 0, 24, 0x0000);
679 rt305x_mii_write(esw, 0, 25, 0x024a);
680 rt305x_mii_write(esw, 0, 26, 0x035a);
681 rt305x_mii_write(esw, 0, 27, 0x02ee);
682 rt305x_mii_write(esw, 0, 28, 0x0233);
683 rt305x_mii_write(esw, 0, 29, 0x000a);
684 rt305x_mii_write(esw, 0, 30, 0x0000);
685 } else {
686 rt305x_mii_write(esw, 0, 31, 0x8000);
687 for (i = 0; i < 5; i++) {
688 if (esw->ports[i].disable) {
689 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
690 } else {
691 rt305x_mii_write(esw, i, MII_BMCR,
692 BMCR_FULLDPLX |
693 BMCR_ANENABLE |
694 BMCR_SPEED100);
695 }
696 /* TX10 waveform coefficient */
697 rt305x_mii_write(esw, i, 26, 0x1601);
698 /* TX100/TX10 AD/DA current bias */
699 rt305x_mii_write(esw, i, 29, 0x7058);
700 /* TX100 slew rate control */
701 rt305x_mii_write(esw, i, 30, 0x0018);
702 }
703
704 /* PHY IOT */
705 /* select global register */
706 rt305x_mii_write(esw, 0, 31, 0x0);
707 /* tune TP_IDL tail and head waveform */
708 rt305x_mii_write(esw, 0, 22, 0x052f);
709 /* set TX10 signal amplitude threshold to minimum */
710 rt305x_mii_write(esw, 0, 17, 0x0fe0);
711 /* set squelch amplitude to higher threshold */
712 rt305x_mii_write(esw, 0, 18, 0x40ba);
713 /* longer TP_IDL tail length */
714 rt305x_mii_write(esw, 0, 14, 0x65);
715 /* select local register */
716 rt305x_mii_write(esw, 0, 31, 0x8000);
717 }
718
719 if (esw->port_map)
720 port_map = esw->port_map;
721 else
722 port_map = RT305X_ESW_PMAP_LLLLLL;
723
724 /* Unused HW feature, but still nice to be consistent here...
725 * This is also exported to userspace ('lan' attribute) so it's
726 * conveniently usable to decide which ports go into the wan vlan by
727 * default.
728 */
729 esw_rmw(esw, RT305X_ESW_REG_SGC2,
730 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
731 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
732
733 /* make the switch leds blink */
734 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
735 esw->ports[i].led = 0x05;
736
737 /* Apply the empty config. */
738 esw_apply_config(&esw->swdev);
739
740 /* Only unmask the port change interrupt */
741 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
742 }
743
744
745 int rt3050_esw_has_carrier(struct fe_priv *priv)
746 {
747 struct rt305x_esw *esw = priv->soc->swpriv;
748 u32 link;
749 int i;
750 bool cpuport;
751
752 link = esw_r32(esw, RT305X_ESW_REG_POA);
753 link >>= RT305X_ESW_POA_LINK_SHIFT;
754 cpuport = link & BIT(RT305X_ESW_PORT6);
755 link &= RT305X_ESW_POA_LINK_MASK;
756 for (i = 0; i <= RT305X_ESW_PORT5; i++) {
757 if (priv->link[i] != (link & BIT(i)))
758 dev_info(esw->dev, "port %d link %s\n", i, link & BIT(i) ? "up" : "down");
759 priv->link[i] = link & BIT(i);
760 }
761
762 return !!link && cpuport;
763 }
764
765 static irqreturn_t esw_interrupt(int irq, void *_esw)
766 {
767 struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
768 u32 status;
769 int i;
770
771 status = esw_r32(esw, RT305X_ESW_REG_ISR);
772 if (status & RT305X_ESW_PORT_ST_CHG) {
773 if (!esw->priv)
774 goto out;
775 if (rt3050_esw_has_carrier(esw->priv))
776 netif_carrier_on(esw->priv->netdev);
777 else
778 netif_carrier_off(esw->priv->netdev);
779 }
780
781 out:
782 esw_w32(esw, status, RT305X_ESW_REG_ISR);
783
784 return IRQ_HANDLED;
785 }
786
787 static int esw_apply_config(struct switch_dev *dev)
788 {
789 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
790 int i;
791 u8 disable = 0;
792 u8 doubletag = 0;
793 u8 en_vlan = 0;
794 u8 untag = 0;
795
796 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
797 u32 vid, vmsc;
798 if (esw->global_vlan_enable) {
799 vid = esw->vlans[i].vid;
800 vmsc = esw->vlans[i].ports;
801 } else {
802 vid = RT305X_ESW_VLAN_NONE;
803 vmsc = RT305X_ESW_PORTS_NONE;
804 }
805 esw_set_vlan_id(esw, i, vid);
806 esw_set_vmsc(esw, i, vmsc);
807 }
808
809 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
810 u32 pvid;
811 disable |= esw->ports[i].disable << i;
812 if (esw->global_vlan_enable) {
813 doubletag |= esw->ports[i].doubletag << i;
814 en_vlan |= 1 << i;
815 untag |= esw->ports[i].untag << i;
816 pvid = esw->ports[i].pvid;
817 } else {
818 int x = esw->alt_vlan_disable ? 0 : 1;
819 doubletag |= x << i;
820 en_vlan |= x << i;
821 untag |= x << i;
822 pvid = 0;
823 }
824 esw_set_pvid(esw, i, pvid);
825 if (i < RT305X_ESW_NUM_LEDS)
826 esw_w32(esw, esw->ports[i].led,
827 RT305X_ESW_REG_P0LED + 4*i);
828 }
829
830 esw_set_gsc(esw);
831 esw_set_port_disable(esw, disable);
832 esw_rmw(esw, RT305X_ESW_REG_SGC2,
833 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
834 RT305X_ESW_SGC2_DOUBLE_TAG_S),
835 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
836 esw_rmw(esw, RT305X_ESW_REG_PFC1,
837 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
838 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
839 esw_rmw(esw, RT305X_ESW_REG_POC2,
840 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
841 untag << RT305X_ESW_POC2_UNTAG_EN_S);
842
843 if (!esw->global_vlan_enable) {
844 /*
845 * Still need to put all ports into vlan 0 or they'll be
846 * isolated.
847 * NOTE: vlan 0 is special, no vlan tag is prepended
848 */
849 esw_set_vlan_id(esw, 0, 0);
850 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
851 }
852
853 return 0;
854 }
855
856 static int esw_reset_switch(struct switch_dev *dev)
857 {
858 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
859
860 esw->global_vlan_enable = 0;
861 memset(esw->ports, 0, sizeof(esw->ports));
862 memset(esw->vlans, 0, sizeof(esw->vlans));
863 esw_hw_init(esw);
864
865 return 0;
866 }
867
868 static int esw_get_vlan_enable(struct switch_dev *dev,
869 const struct switch_attr *attr,
870 struct switch_val *val)
871 {
872 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
873
874 val->value.i = esw->global_vlan_enable;
875
876 return 0;
877 }
878
879 static int esw_set_vlan_enable(struct switch_dev *dev,
880 const struct switch_attr *attr,
881 struct switch_val *val)
882 {
883 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
884
885 esw->global_vlan_enable = val->value.i != 0;
886
887 return 0;
888 }
889
890 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
891 const struct switch_attr *attr,
892 struct switch_val *val)
893 {
894 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
895
896 val->value.i = esw->alt_vlan_disable;
897
898 return 0;
899 }
900
901 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
902 const struct switch_attr *attr,
903 struct switch_val *val)
904 {
905 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
906
907 esw->alt_vlan_disable = val->value.i != 0;
908
909 return 0;
910 }
911
912 static int
913 rt305x_esw_set_bc_status(struct switch_dev *dev,
914 const struct switch_attr *attr,
915 struct switch_val *val)
916 {
917 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
918
919 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
920
921 return 0;
922 }
923
924 static int
925 rt305x_esw_get_bc_status(struct switch_dev *dev,
926 const struct switch_attr *attr,
927 struct switch_val *val)
928 {
929 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
930
931 val->value.i = esw->bc_storm_protect;
932
933 return 0;
934 }
935
936 static int
937 rt305x_esw_set_led_freq(struct switch_dev *dev,
938 const struct switch_attr *attr,
939 struct switch_val *val)
940 {
941 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
942
943 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
944
945 return 0;
946 }
947
948 static int
949 rt305x_esw_get_led_freq(struct switch_dev *dev,
950 const struct switch_attr *attr,
951 struct switch_val *val)
952 {
953 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
954
955 val->value.i = esw->led_frequency;
956
957 return 0;
958 }
959
960 static int esw_get_port_link(struct switch_dev *dev,
961 int port,
962 struct switch_port_link *link)
963 {
964 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
965 u32 speed, poa;
966
967 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
968 return -EINVAL;
969
970 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
971
972 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
973 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
974 if (port < RT305X_ESW_NUM_LEDS) {
975 speed = (poa >> RT305X_ESW_SPD_S) & 1;
976 } else {
977 if (port == RT305X_ESW_NUM_PORTS - 1)
978 poa >>= 1;
979 speed = (poa >> RT305X_ESW_SPD_S) & 3;
980 }
981 switch (speed) {
982 case 0:
983 link->speed = SWITCH_PORT_SPEED_10;
984 break;
985 case 1:
986 link->speed = SWITCH_PORT_SPEED_100;
987 break;
988 case 2:
989 case 3: /* forced gige speed can be 2 or 3 */
990 link->speed = SWITCH_PORT_SPEED_1000;
991 break;
992 default:
993 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
994 break;
995 }
996
997 return 0;
998 }
999
1000 static int esw_get_port_bool(struct switch_dev *dev,
1001 const struct switch_attr *attr,
1002 struct switch_val *val)
1003 {
1004 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1005 int idx = val->port_vlan;
1006 u32 x, reg, shift;
1007
1008 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1009 return -EINVAL;
1010
1011 switch (attr->id) {
1012 case RT305X_ESW_ATTR_PORT_DISABLE:
1013 reg = RT305X_ESW_REG_POC0;
1014 shift = RT305X_ESW_POC0_DIS_PORT_S;
1015 break;
1016 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1017 reg = RT305X_ESW_REG_SGC2;
1018 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1019 break;
1020 case RT305X_ESW_ATTR_PORT_UNTAG:
1021 reg = RT305X_ESW_REG_POC2;
1022 shift = RT305X_ESW_POC2_UNTAG_EN_S;
1023 break;
1024 case RT305X_ESW_ATTR_PORT_LAN:
1025 reg = RT305X_ESW_REG_SGC2;
1026 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1027 if (idx >= RT305X_ESW_NUM_LANWAN)
1028 return -EINVAL;
1029 break;
1030 default:
1031 return -EINVAL;
1032 }
1033
1034 x = esw_r32(esw, reg);
1035 val->value.i = (x >> (idx + shift)) & 1;
1036
1037 return 0;
1038 }
1039
1040 static int esw_set_port_bool(struct switch_dev *dev,
1041 const struct switch_attr *attr,
1042 struct switch_val *val)
1043 {
1044 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1045 int idx = val->port_vlan;
1046
1047 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1048 val->value.i < 0 || val->value.i > 1)
1049 return -EINVAL;
1050
1051 switch (attr->id) {
1052 case RT305X_ESW_ATTR_PORT_DISABLE:
1053 esw->ports[idx].disable = val->value.i;
1054 break;
1055 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1056 esw->ports[idx].doubletag = val->value.i;
1057 break;
1058 case RT305X_ESW_ATTR_PORT_UNTAG:
1059 esw->ports[idx].untag = val->value.i;
1060 break;
1061 default:
1062 return -EINVAL;
1063 }
1064
1065 return 0;
1066 }
1067
1068 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1069 const struct switch_attr *attr,
1070 struct switch_val *val)
1071 {
1072 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1073 int idx = val->port_vlan;
1074 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1075 u32 reg;
1076
1077 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1078 return -EINVAL;
1079 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1080 val->value.i = (reg >> shift) & 0xffff;
1081
1082 return 0;
1083 }
1084
1085 static int
1086 esw_get_port_tr_badgood(struct switch_dev *dev,
1087 const struct switch_attr *attr,
1088 struct switch_val *val)
1089 {
1090 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1091
1092 int idx = val->port_vlan;
1093 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1094 u32 reg;
1095
1096 if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
1097 return -EINVAL;
1098
1099 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1100 return -EINVAL;
1101
1102 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1103 val->value.i = (reg >> shift) & 0xffff;
1104
1105 return 0;
1106 }
1107
1108 static int esw_get_port_led(struct switch_dev *dev,
1109 const struct switch_attr *attr,
1110 struct switch_val *val)
1111 {
1112 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1113 int idx = val->port_vlan;
1114
1115 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1116 idx >= RT305X_ESW_NUM_LEDS)
1117 return -EINVAL;
1118
1119 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1120
1121 return 0;
1122 }
1123
1124 static int esw_set_port_led(struct switch_dev *dev,
1125 const struct switch_attr *attr,
1126 struct switch_val *val)
1127 {
1128 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1129 int idx = val->port_vlan;
1130
1131 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1132 return -EINVAL;
1133
1134 esw->ports[idx].led = val->value.i;
1135
1136 return 0;
1137 }
1138
1139 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1140 {
1141 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1142
1143 if (port >= RT305X_ESW_NUM_PORTS)
1144 return -EINVAL;
1145
1146 *val = esw_get_pvid(esw, port);
1147
1148 return 0;
1149 }
1150
1151 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1152 {
1153 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1154
1155 if (port >= RT305X_ESW_NUM_PORTS)
1156 return -EINVAL;
1157
1158 esw->ports[port].pvid = val;
1159
1160 return 0;
1161 }
1162
1163 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1164 {
1165 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1166 u32 vmsc, poc2;
1167 int vlan_idx = -1;
1168 int i;
1169
1170 val->len = 0;
1171
1172 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1173 return -EINVAL;
1174
1175 /* valid vlan? */
1176 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1177 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1178 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1179 vlan_idx = i;
1180 break;
1181 }
1182 }
1183
1184 if (vlan_idx == -1)
1185 return -EINVAL;
1186
1187 vmsc = esw_get_vmsc(esw, vlan_idx);
1188 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1189
1190 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1191 struct switch_port *p;
1192 int port_mask = 1 << i;
1193
1194 if (!(vmsc & port_mask))
1195 continue;
1196
1197 p = &val->value.ports[val->len++];
1198 p->id = i;
1199 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1200 p->flags = 0;
1201 else
1202 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1203 }
1204
1205 return 0;
1206 }
1207
1208 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1209 {
1210 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1211 int ports;
1212 int vlan_idx = -1;
1213 int i;
1214
1215 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1216 val->len > RT305X_ESW_NUM_PORTS)
1217 return -EINVAL;
1218
1219 /* one of the already defined vlans? */
1220 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1221 if (esw->vlans[i].vid == val->port_vlan &&
1222 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1223 vlan_idx = i;
1224 break;
1225 }
1226 }
1227
1228 /* select a free slot */
1229 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1230 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1231 vlan_idx = i;
1232 }
1233
1234 /* bail if all slots are in use */
1235 if (vlan_idx == -1)
1236 return -EINVAL;
1237
1238 ports = RT305X_ESW_PORTS_NONE;
1239 for (i = 0; i < val->len; i++) {
1240 struct switch_port *p = &val->value.ports[i];
1241 int port_mask = 1 << p->id;
1242 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1243
1244 if (p->id >= RT305X_ESW_NUM_PORTS)
1245 return -EINVAL;
1246
1247 ports |= port_mask;
1248 esw->ports[p->id].untag = untagged;
1249 }
1250 esw->vlans[vlan_idx].ports = ports;
1251 if (ports == RT305X_ESW_PORTS_NONE)
1252 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1253 else
1254 esw->vlans[vlan_idx].vid = val->port_vlan;
1255
1256 return 0;
1257 }
1258
1259 static const struct switch_attr esw_global[] = {
1260 {
1261 .type = SWITCH_TYPE_INT,
1262 .name = "enable_vlan",
1263 .description = "VLAN mode (1:enabled)",
1264 .max = 1,
1265 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1266 .get = esw_get_vlan_enable,
1267 .set = esw_set_vlan_enable,
1268 },
1269 {
1270 .type = SWITCH_TYPE_INT,
1271 .name = "alternate_vlan_disable",
1272 .description = "Use en_vlan instead of doubletag to disable"
1273 " VLAN mode",
1274 .max = 1,
1275 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1276 .get = esw_get_alt_vlan_disable,
1277 .set = esw_set_alt_vlan_disable,
1278 },
1279 {
1280 .type = SWITCH_TYPE_INT,
1281 .name = "bc_storm_protect",
1282 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1283 .max = 3,
1284 .id = RT305X_ESW_ATTR_BC_STATUS,
1285 .get = rt305x_esw_get_bc_status,
1286 .set = rt305x_esw_set_bc_status,
1287 },
1288 {
1289 .type = SWITCH_TYPE_INT,
1290 .name = "led_frequency",
1291 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1292 .max = 3,
1293 .id = RT305X_ESW_ATTR_LED_FREQ,
1294 .get = rt305x_esw_get_led_freq,
1295 .set = rt305x_esw_set_led_freq,
1296 }
1297 };
1298
1299 static const struct switch_attr esw_port[] = {
1300 {
1301 .type = SWITCH_TYPE_INT,
1302 .name = "disable",
1303 .description = "Port state (1:disabled)",
1304 .max = 1,
1305 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1306 .get = esw_get_port_bool,
1307 .set = esw_set_port_bool,
1308 },
1309 {
1310 .type = SWITCH_TYPE_INT,
1311 .name = "doubletag",
1312 .description = "Double tagging for incoming vlan packets "
1313 "(1:enabled)",
1314 .max = 1,
1315 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1316 .get = esw_get_port_bool,
1317 .set = esw_set_port_bool,
1318 },
1319 {
1320 .type = SWITCH_TYPE_INT,
1321 .name = "untag",
1322 .description = "Untag (1:strip outgoing vlan tag)",
1323 .max = 1,
1324 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1325 .get = esw_get_port_bool,
1326 .set = esw_set_port_bool,
1327 },
1328 {
1329 .type = SWITCH_TYPE_INT,
1330 .name = "led",
1331 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1332 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1333 " 8:100mact, 10:blink, 11:off, 12:on)",
1334 .max = 15,
1335 .id = RT305X_ESW_ATTR_PORT_LED,
1336 .get = esw_get_port_led,
1337 .set = esw_set_port_led,
1338 },
1339 {
1340 .type = SWITCH_TYPE_INT,
1341 .name = "lan",
1342 .description = "HW port group (0:wan, 1:lan)",
1343 .max = 1,
1344 .id = RT305X_ESW_ATTR_PORT_LAN,
1345 .get = esw_get_port_bool,
1346 },
1347 {
1348 .type = SWITCH_TYPE_INT,
1349 .name = "recv_bad",
1350 .description = "Receive bad packet counter",
1351 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1352 .get = esw_get_port_recv_badgood,
1353 },
1354 {
1355 .type = SWITCH_TYPE_INT,
1356 .name = "recv_good",
1357 .description = "Receive good packet counter",
1358 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1359 .get = esw_get_port_recv_badgood,
1360 },
1361 {
1362 .type = SWITCH_TYPE_INT,
1363 .name = "tr_bad",
1364
1365 .description = "Transmit bad packet counter. rt5350 only",
1366 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1367 .get = esw_get_port_tr_badgood,
1368 },
1369 {
1370 .type = SWITCH_TYPE_INT,
1371 .name = "tr_good",
1372
1373 .description = "Transmit good packet counter. rt5350 only",
1374 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1375 .get = esw_get_port_tr_badgood,
1376 },
1377 };
1378
1379 static const struct switch_attr esw_vlan[] = {
1380 };
1381
1382 static const struct switch_dev_ops esw_ops = {
1383 .attr_global = {
1384 .attr = esw_global,
1385 .n_attr = ARRAY_SIZE(esw_global),
1386 },
1387 .attr_port = {
1388 .attr = esw_port,
1389 .n_attr = ARRAY_SIZE(esw_port),
1390 },
1391 .attr_vlan = {
1392 .attr = esw_vlan,
1393 .n_attr = ARRAY_SIZE(esw_vlan),
1394 },
1395 .get_vlan_ports = esw_get_vlan_ports,
1396 .set_vlan_ports = esw_set_vlan_ports,
1397 .get_port_pvid = esw_get_port_pvid,
1398 .set_port_pvid = esw_set_port_pvid,
1399 .get_port_link = esw_get_port_link,
1400 .apply_config = esw_apply_config,
1401 .reset_switch = esw_reset_switch,
1402 };
1403
1404 static int esw_probe(struct platform_device *pdev)
1405 {
1406 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1407 struct device_node *np = pdev->dev.of_node;
1408 const __be32 *port_map, *port_disable, *reg_init;
1409 struct rt305x_esw *esw;
1410
1411 esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
1412 if (!esw)
1413 return -ENOMEM;
1414
1415 esw->dev = &pdev->dev;
1416 esw->irq = irq_of_parse_and_map(np, 0);
1417 esw->base = devm_ioremap_resource(&pdev->dev, res);
1418 if (IS_ERR(esw->base))
1419 return PTR_ERR(esw->base);
1420
1421 port_map = of_get_property(np, "mediatek,portmap", NULL);
1422 if (port_map)
1423 esw->port_map = be32_to_cpu(*port_map);
1424
1425 port_disable = of_get_property(np, "mediatek,portdisable", NULL);
1426 if (port_disable)
1427 esw->port_disable = be32_to_cpu(*port_disable);
1428
1429 reg_init = of_get_property(np, "ralink,fct2", NULL);
1430 if (reg_init)
1431 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1432
1433 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1434 if (reg_init)
1435 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1436
1437 reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
1438 if (reg_init)
1439 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1440
1441 reg_init = of_get_property(np, "mediatek,led_source", NULL);
1442 if (reg_init)
1443 esw->reg_led_source = be32_to_cpu(*reg_init);
1444
1445 esw->rst_esw = devm_reset_control_get(&pdev->dev, "esw");
1446 if (IS_ERR(esw->rst_esw))
1447 esw->rst_esw = NULL;
1448 esw->rst_ephy = devm_reset_control_get(&pdev->dev, "ephy");
1449 if (IS_ERR(esw->rst_ephy))
1450 esw->rst_ephy = NULL;
1451
1452 spin_lock_init(&esw->reg_rw_lock);
1453 platform_set_drvdata(pdev, esw);
1454
1455 return 0;
1456 }
1457
1458 static int esw_remove(struct platform_device *pdev)
1459 {
1460 struct rt305x_esw *esw = platform_get_drvdata(pdev);
1461
1462 if (esw) {
1463 esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
1464 platform_set_drvdata(pdev, NULL);
1465 }
1466
1467 return 0;
1468 }
1469
1470 static const struct of_device_id ralink_esw_match[] = {
1471 { .compatible = "ralink,rt3050-esw" },
1472 {},
1473 };
1474 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1475
1476 /* called by the ethernet driver to bound with the switch driver */
1477 int rt3050_esw_init(struct fe_priv *priv)
1478 {
1479 struct device_node *np = priv->switch_np;
1480 struct platform_device *pdev = of_find_device_by_node(np);
1481 struct switch_dev *swdev;
1482 struct rt305x_esw *esw;
1483 const __be32 *rgmii;
1484 int ret;
1485
1486 if (!pdev)
1487 return -ENODEV;
1488
1489 if (!of_device_is_compatible(np, ralink_esw_match->compatible))
1490 return -EINVAL;
1491
1492 esw = platform_get_drvdata(pdev);
1493 if (!esw)
1494 return -EPROBE_DEFER;
1495
1496 priv->soc->swpriv = esw;
1497 esw->priv = priv;
1498
1499 esw_hw_init(esw);
1500
1501 rgmii = of_get_property(np, "ralink,rgmii", NULL);
1502 if (rgmii && be32_to_cpu(*rgmii) == 1) {
1503 /*
1504 * External switch connected to RGMII interface.
1505 * Unregister the switch device after initialization.
1506 */
1507 dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
1508 unregister_switch(&esw->swdev);
1509 platform_set_drvdata(pdev, NULL);
1510 return -ENODEV;
1511 }
1512
1513 swdev = &esw->swdev;
1514 swdev->of_node = pdev->dev.of_node;
1515 swdev->name = "rt305x-esw";
1516 swdev->alias = "rt305x";
1517 swdev->cpu_port = RT305X_ESW_PORT6;
1518 swdev->ports = RT305X_ESW_NUM_PORTS;
1519 swdev->vlans = RT305X_ESW_NUM_VIDS;
1520 swdev->ops = &esw_ops;
1521
1522 ret = register_switch(swdev, NULL);
1523 if (ret < 0) {
1524 dev_err(&pdev->dev, "register_switch failed\n");
1525 return ret;
1526 }
1527
1528 ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
1529 esw);
1530 if (!ret) {
1531 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1532 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1533 }
1534
1535 dev_info(&pdev->dev, "mediatek esw at 0x%08lx, irq %d initialized\n",
1536 esw->base, esw->irq);
1537
1538 return 0;
1539 }
1540
1541 static struct platform_driver esw_driver = {
1542 .probe = esw_probe,
1543 .remove = esw_remove,
1544 .driver = {
1545 .name = "rt3050-esw",
1546 .owner = THIS_MODULE,
1547 .of_match_table = ralink_esw_match,
1548 },
1549 };
1550
1551 module_platform_driver(esw_driver);
1552
1553 MODULE_LICENSE("GPL");
1554 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1555 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1556 MODULE_VERSION(MTK_FE_DRV_VERSION);
Staging tree of Jo-Philipp Wich