target/linux/ramips/files/drivers/dma/mediatek/hsdma-mt7621.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2015, Michael Lee <igvtee@gmail.com>
   4  *  MTK HSDMA support
   5  */
   6
   7 #include <linux/dmaengine.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/err.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/irq.h>
  17 #include <linux/of_dma.h>
  18 #include <linux/reset.h>
  19 #include <linux/of_device.h>
  20
  21 #include "../virt-dma.h"
  22
  23 #define HSDMA_BASE_OFFSET               0x800
  24
  25 #define HSDMA_REG_TX_BASE               0x00
  26 #define HSDMA_REG_TX_CNT                0x04
  27 #define HSDMA_REG_TX_CTX                0x08
  28 #define HSDMA_REG_TX_DTX                0x0c
  29 #define HSDMA_REG_RX_BASE               0x100
  30 #define HSDMA_REG_RX_CNT                0x104
  31 #define HSDMA_REG_RX_CRX                0x108
  32 #define HSDMA_REG_RX_DRX                0x10c
  33 #define HSDMA_REG_INFO                  0x200
  34 #define HSDMA_REG_GLO_CFG               0x204
  35 #define HSDMA_REG_RST_CFG               0x208
  36 #define HSDMA_REG_DELAY_INT             0x20c
  37 #define HSDMA_REG_FREEQ_THRES           0x210
  38 #define HSDMA_REG_INT_STATUS            0x220
  39 #define HSDMA_REG_INT_MASK              0x228
  40 #define HSDMA_REG_SCH_Q01               0x280
  41 #define HSDMA_REG_SCH_Q23               0x284
  42
  43 #define HSDMA_DESCS_MAX                 0xfff
  44 #define HSDMA_DESCS_NUM                 8
  45 #define HSDMA_DESCS_MASK                (HSDMA_DESCS_NUM - 1)
  46 #define HSDMA_NEXT_DESC(x)              (((x) + 1) & HSDMA_DESCS_MASK)
  47
  48 /* HSDMA_REG_INFO */
  49 #define HSDMA_INFO_INDEX_MASK           0xf
  50 #define HSDMA_INFO_INDEX_SHIFT          24
  51 #define HSDMA_INFO_BASE_MASK            0xff
  52 #define HSDMA_INFO_BASE_SHIFT           16
  53 #define HSDMA_INFO_RX_MASK              0xff
  54 #define HSDMA_INFO_RX_SHIFT             8
  55 #define HSDMA_INFO_TX_MASK              0xff
  56 #define HSDMA_INFO_TX_SHIFT             0
  57
  58 /* HSDMA_REG_GLO_CFG */
  59 #define HSDMA_GLO_TX_2B_OFFSET          BIT(31)
  60 #define HSDMA_GLO_CLK_GATE              BIT(30)
  61 #define HSDMA_GLO_BYTE_SWAP             BIT(29)
  62 #define HSDMA_GLO_MULTI_DMA             BIT(10)
  63 #define HSDMA_GLO_TWO_BUF               BIT(9)
  64 #define HSDMA_GLO_32B_DESC              BIT(8)
  65 #define HSDMA_GLO_BIG_ENDIAN            BIT(7)
  66 #define HSDMA_GLO_TX_DONE               BIT(6)
  67 #define HSDMA_GLO_BT_MASK               0x3
  68 #define HSDMA_GLO_BT_SHIFT              4
  69 #define HSDMA_GLO_RX_BUSY               BIT(3)
  70 #define HSDMA_GLO_RX_DMA                BIT(2)
  71 #define HSDMA_GLO_TX_BUSY               BIT(1)
  72 #define HSDMA_GLO_TX_DMA                BIT(0)
  73
  74 #define HSDMA_BT_SIZE_16BYTES           (0 << HSDMA_GLO_BT_SHIFT)
  75 #define HSDMA_BT_SIZE_32BYTES           (1 << HSDMA_GLO_BT_SHIFT)
  76 #define HSDMA_BT_SIZE_64BYTES           (2 << HSDMA_GLO_BT_SHIFT)
  77 #define HSDMA_BT_SIZE_128BYTES          (3 << HSDMA_GLO_BT_SHIFT)
  78
  79 #define HSDMA_GLO_DEFAULT               (HSDMA_GLO_MULTI_DMA | \
  80                 HSDMA_GLO_RX_DMA | HSDMA_GLO_TX_DMA | HSDMA_BT_SIZE_32BYTES)
  81
  82 /* HSDMA_REG_RST_CFG */
  83 #define HSDMA_RST_RX_SHIFT              16
  84 #define HSDMA_RST_TX_SHIFT              0
  85
  86 /* HSDMA_REG_DELAY_INT */
  87 #define HSDMA_DELAY_INT_EN              BIT(15)
  88 #define HSDMA_DELAY_PEND_OFFSET         8
  89 #define HSDMA_DELAY_TIME_OFFSET         0
  90 #define HSDMA_DELAY_TX_OFFSET           16
  91 #define HSDMA_DELAY_RX_OFFSET           0
  92
  93 #define HSDMA_DELAY_INIT(x)             (HSDMA_DELAY_INT_EN | \
  94                 ((x) << HSDMA_DELAY_PEND_OFFSET))
  95 #define HSDMA_DELAY(x)                  ((HSDMA_DELAY_INIT(x) << \
  96                 HSDMA_DELAY_TX_OFFSET) | HSDMA_DELAY_INIT(x))
  97
  98 /* HSDMA_REG_INT_STATUS */
  99 #define HSDMA_INT_DELAY_RX_COH          BIT(31)
 100 #define HSDMA_INT_DELAY_RX_INT          BIT(30)
 101 #define HSDMA_INT_DELAY_TX_COH          BIT(29)
 102 #define HSDMA_INT_DELAY_TX_INT          BIT(28)
 103 #define HSDMA_INT_RX_MASK               0x3
 104 #define HSDMA_INT_RX_SHIFT              16
 105 #define HSDMA_INT_RX_Q0                 BIT(16)
 106 #define HSDMA_INT_TX_MASK               0xf
 107 #define HSDMA_INT_TX_SHIFT              0
 108 #define HSDMA_INT_TX_Q0                 BIT(0)
 109
 110 /* tx/rx dma desc flags */
 111 #define HSDMA_PLEN_MASK                 0x3fff
 112 #define HSDMA_DESC_DONE                 BIT(31)
 113 #define HSDMA_DESC_LS0                  BIT(30)
 114 #define HSDMA_DESC_PLEN0(_x)            (((_x) & HSDMA_PLEN_MASK) << 16)
 115 #define HSDMA_DESC_TAG                  BIT(15)
 116 #define HSDMA_DESC_LS1                  BIT(14)
 117 #define HSDMA_DESC_PLEN1(_x)            ((_x) & HSDMA_PLEN_MASK)
 118
 119 /* align 4 bytes */
 120 #define HSDMA_ALIGN_SIZE                3
 121 /* align size 128bytes */
 122 #define HSDMA_MAX_PLEN                  0x3f80
 123
 124 struct hsdma_desc {
 125         u32 addr0;
 126         u32 flags;
 127         u32 addr1;
 128         u32 unused;
 129 };
 130
 131 struct mtk_hsdma_sg {
 132         dma_addr_t src_addr;
 133         dma_addr_t dst_addr;
 134         u32 len;
 135 };
 136
 137 struct mtk_hsdma_desc {
 138         struct virt_dma_desc vdesc;
 139         unsigned int num_sgs;
 140         struct mtk_hsdma_sg sg[1];
 141 };
 142
 143 struct mtk_hsdma_chan {
 144         struct virt_dma_chan vchan;
 145         unsigned int id;
 146         dma_addr_t desc_addr;
 147         int tx_idx;
 148         int rx_idx;
 149         struct hsdma_desc *tx_ring;
 150         struct hsdma_desc *rx_ring;
 151         struct mtk_hsdma_desc *desc;
 152         unsigned int next_sg;
 153 };
 154
 155 struct mtk_hsdam_engine {
 156         struct dma_device ddev;
 157         struct device_dma_parameters dma_parms;
 158         void __iomem *base;
 159         struct tasklet_struct task;
 160         volatile unsigned long chan_issued;
 161
 162         struct mtk_hsdma_chan chan[1];
 163 };
 164
 165 static inline struct mtk_hsdam_engine *mtk_hsdma_chan_get_dev(struct mtk_hsdma_chan *chan)
 166 {
 167         return container_of(chan->vchan.chan.device, struct mtk_hsdam_engine,
 168                         ddev);
 169 }
 170
 171 static inline struct mtk_hsdma_chan *to_mtk_hsdma_chan(struct dma_chan *c)
 172 {
 173         return container_of(c, struct mtk_hsdma_chan, vchan.chan);
 174 }
 175
 176 static inline struct mtk_hsdma_desc *to_mtk_hsdma_desc(struct virt_dma_desc *vdesc)
 177 {
 178         return container_of(vdesc, struct mtk_hsdma_desc, vdesc);
 179 }
 180
 181 static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg)
 182 {
 183         return readl(hsdma->base + reg);
 184 }
 185
 186 static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
 187                                    unsigned int reg, u32 val)
 188 {
 189         writel(val, hsdma->base + reg);
 190 }
 191
 192 static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
 193                                  struct mtk_hsdma_chan *chan)
 194 {
 195         chan->tx_idx = 0;
 196         chan->rx_idx = HSDMA_DESCS_NUM - 1;
 197
 198         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
 199         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
 200
 201         mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
 202                         0x1 << (chan->id + HSDMA_RST_TX_SHIFT));
 203         mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
 204                         0x1 << (chan->id + HSDMA_RST_RX_SHIFT));
 205 }
 206
 207 static void hsdma_dump_reg(struct mtk_hsdam_engine *hsdma)
 208 {
 209         dev_dbg(hsdma->ddev.dev,
 210                 "tbase %08x, tcnt %08x, tctx %08x, tdtx: %08x, rbase %08x, rcnt %08x, rctx %08x, rdtx %08x\n",
 211                 mtk_hsdma_read(hsdma, HSDMA_REG_TX_BASE),
 212                 mtk_hsdma_read(hsdma, HSDMA_REG_TX_CNT),
 213                 mtk_hsdma_read(hsdma, HSDMA_REG_TX_CTX),
 214                 mtk_hsdma_read(hsdma, HSDMA_REG_TX_DTX),
 215                 mtk_hsdma_read(hsdma, HSDMA_REG_RX_BASE),
 216                 mtk_hsdma_read(hsdma, HSDMA_REG_RX_CNT),
 217                 mtk_hsdma_read(hsdma, HSDMA_REG_RX_CRX),
 218                 mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX));
 219
 220         dev_dbg(hsdma->ddev.dev,
 221                 "info %08x, glo %08x, delay %08x, intr_stat %08x, intr_mask %08x\n",
 222                 mtk_hsdma_read(hsdma, HSDMA_REG_INFO),
 223                 mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG),
 224                 mtk_hsdma_read(hsdma, HSDMA_REG_DELAY_INT),
 225                 mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS),
 226                 mtk_hsdma_read(hsdma, HSDMA_REG_INT_MASK));
 227 }
 228
 229 static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
 230                             struct mtk_hsdma_chan *chan)
 231 {
 232         struct hsdma_desc *tx_desc;
 233         struct hsdma_desc *rx_desc;
 234         int i;
 235
 236         dev_dbg(hsdma->ddev.dev, "tx idx: %d, rx idx: %d\n",
 237                 chan->tx_idx, chan->rx_idx);
 238
 239         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 240                 tx_desc = &chan->tx_ring[i];
 241                 rx_desc = &chan->rx_ring[i];
 242
 243                 dev_dbg(hsdma->ddev.dev,
 244                         "%d tx addr0: %08x, flags %08x, tx addr1: %08x, rx addr0 %08x, flags %08x\n",
 245                         i, tx_desc->addr0, tx_desc->flags,
 246                         tx_desc->addr1, rx_desc->addr0, rx_desc->flags);
 247         }
 248 }
 249
 250 static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
 251                             struct mtk_hsdma_chan *chan)
 252 {
 253         int i;
 254
 255         /* disable dma */
 256         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
 257
 258         /* disable intr */
 259         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
 260
 261         /* init desc value */
 262         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 263                 chan->tx_ring[i].addr0 = 0;
 264                 chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
 265         }
 266         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 267                 chan->rx_ring[i].addr0 = 0;
 268                 chan->rx_ring[i].flags = 0;
 269         }
 270
 271         /* reset */
 272         mtk_hsdma_reset_chan(hsdma, chan);
 273
 274         /* enable intr */
 275         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
 276
 277         /* enable dma */
 278         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
 279 }
 280
 281 static int mtk_hsdma_terminate_all(struct dma_chan *c)
 282 {
 283         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 284         struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
 285         unsigned long timeout;
 286         LIST_HEAD(head);
 287
 288         spin_lock_bh(&chan->vchan.lock);
 289         chan->desc = NULL;
 290         clear_bit(chan->id, &hsdma->chan_issued);
 291         vchan_get_all_descriptors(&chan->vchan, &head);
 292         spin_unlock_bh(&chan->vchan.lock);
 293
 294         vchan_dma_desc_free_list(&chan->vchan, &head);
 295
 296         /* wait dma transfer complete */
 297         timeout = jiffies + msecs_to_jiffies(2000);
 298         while (mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG) &
 299                         (HSDMA_GLO_RX_BUSY | HSDMA_GLO_TX_BUSY)) {
 300                 if (time_after_eq(jiffies, timeout)) {
 301                         hsdma_dump_desc(hsdma, chan);
 302                         mtk_hsdma_reset(hsdma, chan);
 303                         dev_err(hsdma->ddev.dev, "timeout, reset it\n");
 304                         break;
 305                 }
 306                 cpu_relax();
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
 313                                     struct mtk_hsdma_chan *chan)
 314 {
 315         dma_addr_t src, dst;
 316         size_t len, tlen;
 317         struct hsdma_desc *tx_desc, *rx_desc;
 318         struct mtk_hsdma_sg *sg;
 319         unsigned int i;
 320         int rx_idx;
 321
 322         sg = &chan->desc->sg[0];
 323         len = sg->len;
 324         chan->desc->num_sgs = DIV_ROUND_UP(len, HSDMA_MAX_PLEN);
 325
 326         /* tx desc */
 327         src = sg->src_addr;
 328         for (i = 0; i < chan->desc->num_sgs; i++) {
 329                 tx_desc = &chan->tx_ring[chan->tx_idx];
 330
 331                 if (len > HSDMA_MAX_PLEN)
 332                         tlen = HSDMA_MAX_PLEN;
 333                 else
 334                         tlen = len;
 335
 336                 if (i & 0x1) {
 337                         tx_desc->addr1 = src;
 338                         tx_desc->flags |= HSDMA_DESC_PLEN1(tlen);
 339                 } else {
 340                         tx_desc->addr0 = src;
 341                         tx_desc->flags = HSDMA_DESC_PLEN0(tlen);
 342
 343                         /* update index */
 344                         chan->tx_idx = HSDMA_NEXT_DESC(chan->tx_idx);
 345                 }
 346
 347                 src += tlen;
 348                 len -= tlen;
 349         }
 350         if (i & 0x1)
 351                 tx_desc->flags |= HSDMA_DESC_LS0;
 352         else
 353                 tx_desc->flags |= HSDMA_DESC_LS1;
 354
 355         /* rx desc */
 356         rx_idx = HSDMA_NEXT_DESC(chan->rx_idx);
 357         len = sg->len;
 358         dst = sg->dst_addr;
 359         for (i = 0; i < chan->desc->num_sgs; i++) {
 360                 rx_desc = &chan->rx_ring[rx_idx];
 361                 if (len > HSDMA_MAX_PLEN)
 362                         tlen = HSDMA_MAX_PLEN;
 363                 else
 364                         tlen = len;
 365
 366                 rx_desc->addr0 = dst;
 367                 rx_desc->flags = HSDMA_DESC_PLEN0(tlen);
 368
 369                 dst += tlen;
 370                 len -= tlen;
 371
 372                 /* update index */
 373                 rx_idx = HSDMA_NEXT_DESC(rx_idx);
 374         }
 375
 376         /* make sure desc and index all up to date */
 377         wmb();
 378         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
 379
 380         return 0;
 381 }
 382
 383 static int gdma_next_desc(struct mtk_hsdma_chan *chan)
 384 {
 385         struct virt_dma_desc *vdesc;
 386
 387         vdesc = vchan_next_desc(&chan->vchan);
 388         if (!vdesc) {
 389                 chan->desc = NULL;
 390                 return 0;
 391         }
 392         chan->desc = to_mtk_hsdma_desc(vdesc);
 393         chan->next_sg = 0;
 394
 395         return 1;
 396 }
 397
 398 static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
 399                                 struct mtk_hsdma_chan *chan)
 400 {
 401         struct mtk_hsdma_desc *desc;
 402         int chan_issued;
 403
 404         chan_issued = 0;
 405         spin_lock_bh(&chan->vchan.lock);
 406         desc = chan->desc;
 407         if (likely(desc)) {
 408                 if (chan->next_sg == desc->num_sgs) {
 409                         list_del(&desc->vdesc.node);
 410                         vchan_cookie_complete(&desc->vdesc);
 411                         chan_issued = gdma_next_desc(chan);
 412                 }
 413         } else {
 414                 dev_dbg(hsdma->ddev.dev, "no desc to complete\n");
 415         }
 416
 417         if (chan_issued)
 418                 set_bit(chan->id, &hsdma->chan_issued);
 419         spin_unlock_bh(&chan->vchan.lock);
 420 }
 421
 422 static irqreturn_t mtk_hsdma_irq(int irq, void *devid)
 423 {
 424         struct mtk_hsdam_engine *hsdma = devid;
 425         u32 status;
 426
 427         status = mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS);
 428         if (unlikely(!status))
 429                 return IRQ_NONE;
 430
 431         if (likely(status & HSDMA_INT_RX_Q0))
 432                 tasklet_schedule(&hsdma->task);
 433         else
 434                 dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n", status);
 435         /* clean intr bits */
 436         mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
 437
 438         return IRQ_HANDLED;
 439 }
 440
 441 static void mtk_hsdma_issue_pending(struct dma_chan *c)
 442 {
 443         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 444         struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
 445
 446         spin_lock_bh(&chan->vchan.lock);
 447         if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
 448                 if (gdma_next_desc(chan)) {
 449                         set_bit(chan->id, &hsdma->chan_issued);
 450                         tasklet_schedule(&hsdma->task);
 451                 } else {
 452                         dev_dbg(hsdma->ddev.dev, "no desc to issue\n");
 453                 }
 454         }
 455         spin_unlock_bh(&chan->vchan.lock);
 456 }
 457
 458 static struct dma_async_tx_descriptor *mtk_hsdma_prep_dma_memcpy(
 459                 struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
 460                 size_t len, unsigned long flags)
 461 {
 462         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 463         struct mtk_hsdma_desc *desc;
 464
 465         if (len <= 0)
 466                 return NULL;
 467
 468         desc = kzalloc(sizeof(*desc), GFP_ATOMIC);
 469         if (!desc) {
 470                 dev_err(c->device->dev, "alloc memcpy decs error\n");
 471                 return NULL;
 472         }
 473
 474         desc->sg[0].src_addr = src;
 475         desc->sg[0].dst_addr = dest;
 476         desc->sg[0].len = len;
 477
 478         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 479 }
 480
 481 static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
 482                                            dma_cookie_t cookie,
 483                                            struct dma_tx_state *state)
 484 {
 485         return dma_cookie_status(c, cookie, state);
 486 }
 487
 488 static void mtk_hsdma_free_chan_resources(struct dma_chan *c)
 489 {
 490         vchan_free_chan_resources(to_virt_chan(c));
 491 }
 492
 493 static void mtk_hsdma_desc_free(struct virt_dma_desc *vdesc)
 494 {
 495         kfree(container_of(vdesc, struct mtk_hsdma_desc, vdesc));
 496 }
 497
 498 static void mtk_hsdma_tx(struct mtk_hsdam_engine *hsdma)
 499 {
 500         struct mtk_hsdma_chan *chan;
 501
 502         if (test_and_clear_bit(0, &hsdma->chan_issued)) {
 503                 chan = &hsdma->chan[0];
 504                 if (chan->desc)
 505                         mtk_hsdma_start_transfer(hsdma, chan);
 506                 else
 507                         dev_dbg(hsdma->ddev.dev, "chan 0 no desc to issue\n");
 508         }
 509 }
 510
 511 static void mtk_hsdma_rx(struct mtk_hsdam_engine *hsdma)
 512 {
 513         struct mtk_hsdma_chan *chan;
 514         int next_idx, drx_idx, cnt;
 515
 516         chan = &hsdma->chan[0];
 517         next_idx = HSDMA_NEXT_DESC(chan->rx_idx);
 518         drx_idx = mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX);
 519
 520         cnt = (drx_idx - next_idx) & HSDMA_DESCS_MASK;
 521         if (!cnt)
 522                 return;
 523
 524         chan->next_sg += cnt;
 525         chan->rx_idx = (chan->rx_idx + cnt) & HSDMA_DESCS_MASK;
 526
 527         /* update rx crx */
 528         wmb();
 529         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
 530
 531         mtk_hsdma_chan_done(hsdma, chan);
 532 }
 533
 534 static void mtk_hsdma_tasklet(struct tasklet_struct *t)
 535 {
 536         struct mtk_hsdam_engine *hsdma = from_tasklet(hsdma, t, task);
 537
 538         mtk_hsdma_rx(hsdma);
 539         mtk_hsdma_tx(hsdma);
 540 }
 541
 542 static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
 543                                 struct mtk_hsdma_chan *chan)
 544 {
 545         int i;
 546
 547         chan->tx_ring = dma_alloc_coherent(hsdma->ddev.dev,
 548                                            2 * HSDMA_DESCS_NUM *
 549                                            sizeof(*chan->tx_ring),
 550                         &chan->desc_addr, GFP_ATOMIC | __GFP_ZERO);
 551         if (!chan->tx_ring)
 552                 goto no_mem;
 553
 554         chan->rx_ring = &chan->tx_ring[HSDMA_DESCS_NUM];
 555
 556         /* init tx ring value */
 557         for (i = 0; i < HSDMA_DESCS_NUM; i++)
 558                 chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
 559
 560         return 0;
 561 no_mem:
 562         return -ENOMEM;
 563 }
 564
 565 static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
 566                                 struct mtk_hsdma_chan *chan)
 567 {
 568         if (chan->tx_ring) {
 569                 dma_free_coherent(hsdma->ddev.dev,
 570                                   2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
 571                                   chan->tx_ring, chan->desc_addr);
 572                 chan->tx_ring = NULL;
 573                 chan->rx_ring = NULL;
 574         }
 575 }
 576
 577 static int mtk_hsdma_init(struct mtk_hsdam_engine *hsdma)
 578 {
 579         struct mtk_hsdma_chan *chan;
 580         int ret;
 581         u32 reg;
 582
 583         /* init desc */
 584         chan = &hsdma->chan[0];
 585         ret = mtk_hsdam_alloc_desc(hsdma, chan);
 586         if (ret)
 587                 return ret;
 588
 589         /* tx */
 590         mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, chan->desc_addr);
 591         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, HSDMA_DESCS_NUM);
 592         /* rx */
 593         mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, chan->desc_addr +
 594                         (sizeof(struct hsdma_desc) * HSDMA_DESCS_NUM));
 595         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, HSDMA_DESCS_NUM);
 596         /* reset */
 597         mtk_hsdma_reset_chan(hsdma, chan);
 598
 599         /* enable rx intr */
 600         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
 601
 602         /* enable dma */
 603         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
 604
 605         /* hardware info */
 606         reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
 607         dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
 608                  (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
 609                  (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
 610
 611         hsdma_dump_reg(hsdma);
 612
 613         return ret;
 614 }
 615
 616 static void mtk_hsdma_uninit(struct mtk_hsdam_engine *hsdma)
 617 {
 618         struct mtk_hsdma_chan *chan;
 619
 620         /* disable dma */
 621         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
 622
 623         /* disable intr */
 624         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
 625
 626         /* free desc */
 627         chan = &hsdma->chan[0];
 628         mtk_hsdam_free_desc(hsdma, chan);
 629
 630         /* tx */
 631         mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, 0);
 632         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, 0);
 633         /* rx */
 634         mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, 0);
 635         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, 0);
 636         /* reset */
 637         mtk_hsdma_reset_chan(hsdma, chan);
 638 }
 639
 640 static const struct of_device_id mtk_hsdma_of_match[] = {
 641         { .compatible = "mediatek,mt7621-hsdma" },
 642         { },
 643 };
 644
 645 static int mtk_hsdma_probe(struct platform_device *pdev)
 646 {
 647         const struct of_device_id *match;
 648         struct mtk_hsdma_chan *chan;
 649         struct mtk_hsdam_engine *hsdma;
 650         struct dma_device *dd;
 651         int ret;
 652         int irq;
 653         void __iomem *base;
 654
 655         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 656         if (ret)
 657                 return ret;
 658
 659         match = of_match_device(mtk_hsdma_of_match, &pdev->dev);
 660         if (!match)
 661                 return -EINVAL;
 662
 663         hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
 664         if (!hsdma)
 665                 return -EINVAL;
 666
 667         base = devm_platform_ioremap_resource(pdev, 0);
 668         if (IS_ERR(base))
 669                 return PTR_ERR(base);
 670         hsdma->base = base + HSDMA_BASE_OFFSET;
 671         tasklet_setup(&hsdma->task, mtk_hsdma_tasklet);
 672
 673         irq = platform_get_irq(pdev, 0);
 674         if (irq < 0)
 675                 return -EINVAL;
 676         ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
 677                                0, dev_name(&pdev->dev), hsdma);
 678         if (ret) {
 679                 dev_err(&pdev->dev, "failed to request irq\n");
 680                 return ret;
 681         }
 682
 683         ret = device_reset(&pdev->dev);
 684         if (ret)
 685                 dev_err(&pdev->dev, "failed to reset device\n");
 686
 687         dd = &hsdma->ddev;
 688         dma_cap_set(DMA_MEMCPY, dd->cap_mask);
 689         dd->copy_align = HSDMA_ALIGN_SIZE;
 690         dd->device_free_chan_resources = mtk_hsdma_free_chan_resources;
 691         dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy;
 692         dd->device_terminate_all = mtk_hsdma_terminate_all;
 693         dd->device_tx_status = mtk_hsdma_tx_status;
 694         dd->device_issue_pending = mtk_hsdma_issue_pending;
 695         dd->dev = &pdev->dev;
 696         dd->dev->dma_parms = &hsdma->dma_parms;
 697         dma_set_max_seg_size(dd->dev, HSDMA_MAX_PLEN);
 698         INIT_LIST_HEAD(&dd->channels);
 699
 700         chan = &hsdma->chan[0];
 701         chan->id = 0;
 702         chan->vchan.desc_free = mtk_hsdma_desc_free;
 703         vchan_init(&chan->vchan, dd);
 704
 705         /* init hardware */
 706         ret = mtk_hsdma_init(hsdma);
 707         if (ret) {
 708                 dev_err(&pdev->dev, "failed to alloc ring descs\n");
 709                 return ret;
 710         }
 711
 712         ret = dma_async_device_register(dd);
 713         if (ret) {
 714                 dev_err(&pdev->dev, "failed to register dma device\n");
 715                 goto err_uninit_hsdma;
 716         }
 717
 718         ret = of_dma_controller_register(pdev->dev.of_node,
 719                                          of_dma_xlate_by_chan_id, hsdma);
 720         if (ret) {
 721                 dev_err(&pdev->dev, "failed to register of dma controller\n");
 722                 goto err_unregister;
 723         }
 724
 725         platform_set_drvdata(pdev, hsdma);
 726
 727         return 0;
 728
 729 err_unregister:
 730         dma_async_device_unregister(dd);
 731 err_uninit_hsdma:
 732         mtk_hsdma_uninit(hsdma);
 733         return ret;
 734 }
 735
 736 static int mtk_hsdma_remove(struct platform_device *pdev)
 737 {
 738         struct mtk_hsdam_engine *hsdma = platform_get_drvdata(pdev);
 739
 740         mtk_hsdma_uninit(hsdma);
 741
 742         of_dma_controller_free(pdev->dev.of_node);
 743         dma_async_device_unregister(&hsdma->ddev);
 744
 745         return 0;
 746 }
 747
 748 static struct platform_driver mtk_hsdma_driver = {
 749         .probe = mtk_hsdma_probe,
 750         .remove = mtk_hsdma_remove,
 751         .driver = {
 752                 .name = KBUILD_MODNAME,
 753                 .of_match_table = mtk_hsdma_of_match,
 754         },
 755 };
 756 module_platform_driver(mtk_hsdma_driver);
 757
 758 MODULE_AUTHOR("Michael Lee <igvtee@gmail.com>");
 759 MODULE_DESCRIPTION("MTK HSDMA driver");
 760 MODULE_LICENSE("GPL v2");