target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h

   1 /*
   2  * Ralink RT3662/RT3883 SoC specific definitions
   3  *
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #ifndef _RT3883_H_
  14 #define _RT3883_H_
  15
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18
  19 void rt3883_detect_sys_type(void);
  20
  21 #define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024)
  22 #define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024)
  23
  24 #define RT3883_CPU_IRQ_BASE     0
  25 #define RT3883_CPU_IRQ_COUNT    8
  26 #define RT3883_INTC_IRQ_BASE    (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT)
  27 #define RT3883_INTC_IRQ_COUNT   32
  28 #define RT3883_GPIO_IRQ_BASE    (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT)
  29 #define RT3883_GPIO_IRQ_COUNT   96
  30 #define RT3883_PCI_IRQ_BASE     (RT3883_GPIO_IRQ_BASE + RT3883_GPIO_IRQ_COUNT)
  31 #define RT3883_PCI_IRQ_COUNT    3
  32
  33 #define RT3883_CPU_IRQ_INTC     (RT3883_CPU_IRQ_BASE + 2)
  34 #define RT3883_CPU_IRQ_PCI      (RT3883_CPU_IRQ_BASE + 4)
  35 #define RT3883_CPU_IRQ_FE       (RT3883_CPU_IRQ_BASE + 5)
  36 #define RT3883_CPU_IRQ_WLAN     (RT3883_CPU_IRQ_BASE + 6)
  37 #define RT3883_CPU_IRQ_COUNTER  (RT3883_CPU_IRQ_BASE + 7)
  38
  39 #define RT3883_INTC_IRQ_SYSCTL  (RT3883_INTC_IRQ_BASE + 0)
  40 #define RT3883_INTC_IRQ_TIMER0  (RT3883_INTC_IRQ_BASE + 1)
  41 #define RT3883_INTC_IRQ_TIMER1  (RT3883_INTC_IRQ_BASE + 2)
  42 #define RT3883_INTC_IRQ_IA      (RT3883_INTC_IRQ_BASE + 3)
  43 #define RT3883_INTC_IRQ_PCM     (RT3883_INTC_IRQ_BASE + 4)
  44 #define RT3883_INTC_IRQ_UART0   (RT3883_INTC_IRQ_BASE + 5)
  45 #define RT3883_INTC_IRQ_PIO     (RT3883_INTC_IRQ_BASE + 6)
  46 #define RT3883_INTC_IRQ_DMA     (RT3883_INTC_IRQ_BASE + 7)
  47 #define RT3883_INTC_IRQ_NAND    (RT3883_INTC_IRQ_BASE + 8)
  48 #define RT3883_INTC_IRQ_PERFC   (RT3883_INTC_IRQ_BASE + 9)
  49 #define RT3883_INTC_IRQ_I2S     (RT3883_INTC_IRQ_BASE + 10)
  50 #define RT3883_INTC_IRQ_UART1   (RT3883_INTC_IRQ_BASE + 12)
  51 #define RT3883_INTC_IRQ_UHST    (RT3883_INTC_IRQ_BASE + 18)
  52 #define RT3883_INTC_IRQ_UDEV    (RT3883_INTC_IRQ_BASE + 19)
  53
  54 #define RT3883_PCI_IRQ_PCI0     (RT3883_PCI_IRQ_BASE + 0)
  55 #define RT3883_PCI_IRQ_PCI1     (RT3883_PCI_IRQ_BASE + 1)
  56 #define RT3883_PCI_IRQ_PCIE     (RT3883_PCI_IRQ_BASE + 2)
  57
  58 extern void __iomem *rt3883_sysc_base;
  59 extern void __iomem *rt3883_memc_base;
  60
  61 static inline void rt3883_sysc_wr(u32 val, unsigned reg)
  62 {
  63         __raw_writel(val, rt3883_sysc_base + reg);
  64 }
  65
  66 static inline u32 rt3883_sysc_rr(unsigned reg)
  67 {
  68         return __raw_readl(rt3883_sysc_base + reg);
  69 }
  70
  71 static inline void rt3883_memc_wr(u32 val, unsigned reg)
  72 {
  73         __raw_writel(val, rt3883_memc_base + reg);
  74 }
  75
  76 static inline u32 rt3883_memc_rr(unsigned reg)
  77 {
  78         return __raw_readl(rt3883_memc_base + reg);
  79 }
  80
  81 #define RT3883_GPIO_I2C_SD      1
  82 #define RT3883_GPIO_I2C_SCLK    2
  83 #define RT3883_GPIO_SPI_CS0     3
  84 #define RT3883_GPIO_SPI_CLK     4
  85 #define RT3883_GPIO_SPI_MOSI    5
  86 #define RT3883_GPIO_SPI_MISO    6
  87 /* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
  88 #define RT3883_GPIO_7           7
  89 #define RT3883_GPIO_8           8
  90 #define RT3883_GPIO_9           9
  91 #define RT3883_GPIO_10          10
  92 #define RT3883_GPIO_11          11
  93 #define RT3883_GPIO_12          12
  94 #define RT3883_GPIO_13          13
  95 #define RT3883_GPIO_14          14
  96 #define RT3883_GPIO_UART1_TXD   15
  97 #define RT3883_GPIO_UART1_RXD   16
  98 #define RT3883_GPIO_JTAG_TDO    17
  99 #define RT3883_GPIO_JTAG_TDI    18
 100 #define RT3883_GPIO_JTAG_TMS    19
 101 #define RT3883_GPIO_JTAG_TCLK   20
 102 #define RT3883_GPIO_JTAG_TRST_N 21
 103 #define RT3883_GPIO_MDIO_MDC    22
 104 #define RT3883_GPIO_MDIO_MDIO   23
 105 #define RT3883_GPIO_LNA_PE_A0   32
 106 #define RT3883_GPIO_LNA_PE_A1   33
 107 #define RT3883_GPIO_LNA_PE_A2   34
 108 #define RT3883_GPIO_LNA_PE_G0   35
 109 #define RT3883_GPIO_LNA_PE_G1   36
 110 #define RT3883_GPIO_LNA_PE_G2   37
 111 #define RT3883_GPIO_PCI_AD0     40
 112 #define RT3883_GPIO_PCI_AD31    71
 113 #define RT3883_GPIO_GE2_TXD0    72
 114 #define RT3883_GPIO_GE2_TXD1    73
 115 #define RT3883_GPIO_GE2_TXD2    74
 116 #define RT3883_GPIO_GE2_TXD3    75
 117 #define RT3883_GPIO_GE2_TXEN    76
 118 #define RT3883_GPIO_GE2_TXCLK   77
 119 #define RT3883_GPIO_GE2_RXD0    78
 120 #define RT3883_GPIO_GE2_RXD1    79
 121 #define RT3883_GPIO_GE2_RXD2    80
 122 #define RT3883_GPIO_GE2_RXD3    81
 123 #define RT3883_GPIO_GE2_RXDV    82
 124 #define RT3883_GPIO_GE2_RXCLK   83
 125 #define RT3883_GPIO_GE1_TXD0    84
 126 #define RT3883_GPIO_GE1_TXD1    85
 127 #define RT3883_GPIO_GE1_TXD2    86
 128 #define RT3883_GPIO_GE1_TXD3    87
 129 #define RT3883_GPIO_GE1_TXEN    88
 130 #define RT3883_GPIO_GE1_TXCLK   89
 131 #define RT3883_GPIO_GE1_RXD0    90
 132 #define RT3883_GPIO_GE1_RXD1    91
 133 #define RT3883_GPIO_GE1_RXD2    92
 134 #define RT3883_GPIO_GE1_RXD3    93
 135 #define RT3883_GPIO_GE1_RXDV    94
 136 #define RT3883_GPIO_GE1_RXCLK   95
 137
 138 void rt3883_gpio_init(u32 mode);
 139
 140 #define RT3883_PCI_MODE_PCI     0x01
 141 #define RT3883_PCI_MODE_PCIE    0x02
 142 #define RT3883_PCI_MODE_BOTH    (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
 143
 144 struct pci_dev;
 145
 146 #ifdef CONFIG_PCI
 147 void rt3883_pci_init(unsigned mode);
 148 void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *));
 149 #else
 150 static inline void rt3883_pci_init(unsigned mode) {}
 151 static inline void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)) {}
 152 #endif /* CONFIG_PCI */
 153
 154 #endif /* _RT3883_H_ */