target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/clock/mt7621-clk.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "mediatek,mt7621-soc";
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "mips,mips1004Kc";
  16                         reg = <0>;
  17                 };
  18
  19                 cpu@1 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips1004Kc";
  22                         reg = <1>;
  23                 };
  24         };
  25
  26         cpuintc: cpuintc {
  27                 #address-cells = <0>;
  28                 #interrupt-cells = <1>;
  29                 interrupt-controller;
  30                 compatible = "mti,cpu-interrupt-controller";
  31         };
  32
  33         aliases {
  34                 serial0 = &uartlite;
  35         };
  36
  37         pll: pll {
  38                 compatible = "mediatek,mt7621-pll", "syscon";
  39
  40                 #clock-cells = <1>;
  41                 clock-output-names = "cpu", "bus";
  42         };
  43
  44         sysclock: sysclock {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47
  48                 /* FIXME: there should be way to detect this */
  49                 clock-frequency = <50000000>;
  50         };
  51
  52
  53
  54         palmbus: palmbus@1E000000 {
  55                 compatible = "palmbus";
  56                 reg = <0x1E000000 0x100000>;
  57                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  58
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61
  62                 sysc: sysc@0 {
  63                         compatible = "mtk,mt7621-sysc";
  64                         reg = <0x0 0x100>;
  65                 };
  66
  67                 wdt: wdt@100 {
  68                         compatible = "mediatek,mt7621-wdt";
  69                         reg = <0x100 0x100>;
  70                 };
  71
  72                 gpio@600 {
  73                         #address-cells = <1>;
  74                         #size-cells = <0>;
  75
  76                         compatible = "mtk,mt7621-gpio";
  77                         reg = <0x600 0x100>;
  78
  79                         interrupt-parent = <&gic>;
  80                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  81
  82                         gpio0: bank@0 {
  83                                 reg = <0>;
  84                                 compatible = "mtk,mt7621-gpio-bank";
  85                                 gpio-controller;
  86                                 #gpio-cells = <2>;
  87                         };
  88
  89                         gpio1: bank@1 {
  90                                 reg = <1>;
  91                                 compatible = "mtk,mt7621-gpio-bank";
  92                                 gpio-controller;
  93                                 #gpio-cells = <2>;
  94                         };
  95
  96                         gpio2: bank@2 {
  97                                 reg = <2>;
  98                                 compatible = "mtk,mt7621-gpio-bank";
  99                                 gpio-controller;
 100                                 #gpio-cells = <2>;
 101                         };
 102                 };
 103
 104                 i2c: i2c@900 {
 105                         compatible = "mediatek,mt7621-i2c";
 106                         reg = <0x900 0x100>;
 107
 108                         clocks = <&sysclock>;
 109
 110                         resets = <&rstctrl 16>;
 111                         reset-names = "i2c";
 112
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115
 116                         status = "disabled";
 117
 118                         pinctrl-names = "default";
 119                         pinctrl-0 = <&i2c_pins>;
 120                 };
 121
 122                 i2s: i2s@a00 {
 123                         compatible = "mediatek,mt7621-i2s";
 124                         reg = <0xa00 0x100>;
 125
 126                         clocks = <&sysclock>;
 127
 128                         resets = <&rstctrl 17>;
 129                         reset-names = "i2s";
 130
 131                         interrupt-parent = <&gic>;
 132                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 133
 134                         txdma-req = <2>;
 135                         rxdma-req = <3>;
 136
 137                         dmas = <&gdma 4>,
 138                                 <&gdma 6>;
 139                         dma-names = "tx", "rx";
 140
 141                         status = "disabled";
 142                 };
 143
 144                 systick: systick@500 {
 145                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 146                         reg = <0x500 0x10>;
 147
 148                         resets = <&rstctrl 28>;
 149                         reset-names = "intc";
 150
 151                         interrupt-parent = <&gic>;
 152                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 153                 };
 154
 155                 memc: memc@5000 {
 156                         compatible = "mtk,mt7621-memc";
 157                         reg = <0x5000 0x1000>;
 158                 };
 159
 160                 cpc: cpc@1fbf0000 {
 161                         compatible = "mtk,mt7621-cpc";
 162                         reg = <0x1fbf0000 0x8000>;
 163                 };
 164
 165                 mc: mc@1fbf8000 {
 166                         compatible = "mtk,mt7621-mc";
 167                         reg = <0x1fbf8000 0x8000>;
 168                 };
 169
 170                 uartlite: uartlite@c00 {
 171                         compatible = "ns16550a";
 172                         reg = <0xc00 0x100>;
 173
 174                         clock-frequency = <50000000>;
 175
 176                         interrupt-parent = <&gic>;
 177                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 178
 179                         reg-shift = <2>;
 180                         reg-io-width = <4>;
 181                         no-loopback-test;
 182                 };
 183
 184                 uartlite2: uartlite2@d00 {
 185                         compatible = "ns16550a";
 186                         reg = <0xd00 0x100>;
 187
 188                         clock-frequency = <50000000>;
 189
 190                         interrupt-parent = <&gic>;
 191                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 192
 193                         reg-shift = <2>;
 194                         reg-io-width = <4>;
 195
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&uart2_pins>;
 198
 199                         status = "disabled";
 200                 };
 201
 202                 uartlite3: uartlite3@e00 {
 203                         compatible = "ns16550a";
 204                         reg = <0xe00 0x100>;
 205
 206                         clock-frequency = <50000000>;
 207
 208                         interrupt-parent = <&gic>;
 209                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 210
 211                         reg-shift = <2>;
 212                         reg-io-width = <4>;
 213
 214                         pinctrl-names = "default";
 215                         pinctrl-0 = <&uart3_pins>;
 216
 217                         status = "disabled";
 218                 };
 219
 220                 spi0: spi@b00 {
 221                         status = "disabled";
 222
 223                         compatible = "ralink,mt7621-spi";
 224                         reg = <0xb00 0x100>;
 225
 226                         clocks = <&pll MT7621_CLK_BUS>;
 227
 228                         resets = <&rstctrl 18>;
 229                         reset-names = "spi";
 230
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233
 234                         pinctrl-names = "default";
 235                         pinctrl-0 = <&spi_pins>;
 236                 };
 237
 238                 gdma: gdma@2800 {
 239                         compatible = "ralink,rt3883-gdma";
 240                         reg = <0x2800 0x800>;
 241
 242                         resets = <&rstctrl 14>;
 243                         reset-names = "dma";
 244
 245                         interrupt-parent = <&gic>;
 246                         interrupts = <0 13 4>;
 247
 248                         #dma-cells = <1>;
 249                         #dma-channels = <16>;
 250                         #dma-requests = <16>;
 251
 252                         status = "disabled";
 253                 };
 254
 255                 hsdma: hsdma@7000 {
 256                         compatible = "mediatek,mt7621-hsdma";
 257                         reg = <0x7000 0x1000>;
 258
 259                         resets = <&rstctrl 5>;
 260                         reset-names = "hsdma";
 261
 262                         interrupt-parent = <&gic>;
 263                         interrupts = <0 11 4>;
 264
 265                         #dma-cells = <1>;
 266                         #dma-channels = <1>;
 267                         #dma-requests = <1>;
 268
 269                         status = "disabled";
 270                 };
 271         };
 272
 273         pinctrl: pinctrl {
 274                 compatible = "ralink,rt2880-pinmux";
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&state_default>;
 277
 278                 state_default: pinctrl0 {
 279                 };
 280
 281                 i2c_pins: i2c_pins {
 282                         i2c_pins {
 283                                 ralink,group = "i2c";
 284                                 ralink,function = "i2c";
 285                         };
 286                 };
 287
 288                 spi_pins: spi_pins {
 289                         spi_pins {
 290                                 ralink,group = "spi";
 291                                 ralink,function = "spi";
 292                         };
 293                 };
 294
 295                 uart1_pins: uart1 {
 296                         uart1 {
 297                                 ralink,group = "uart1";
 298                                 ralink,function = "uart1";
 299                         };
 300                 };
 301
 302                 uart2_pins: uart2 {
 303                         uart2 {
 304                                 ralink,group = "uart2";
 305                                 ralink,function = "uart2";
 306                         };
 307                 };
 308
 309                 uart3_pins: uart3 {
 310                         uart3 {
 311                                 ralink,group = "uart3";
 312                                 ralink,function = "uart3";
 313                         };
 314                 };
 315
 316                 rgmii1_pins: rgmii1 {
 317                         rgmii1 {
 318                                 ralink,group = "rgmii1";
 319                                 ralink,function = "rgmii1";
 320                         };
 321                 };
 322
 323                 rgmii2_pins: rgmii2 {
 324                         rgmii2 {
 325                                 ralink,group = "rgmii2";
 326                                 ralink,function = "rgmii2";
 327                         };
 328                 };
 329
 330                 mdio_pins: mdio {
 331                         mdio {
 332                                 ralink,group = "mdio";
 333                                 ralink,function = "mdio";
 334                         };
 335                 };
 336
 337                 pcie_pins: pcie {
 338                         pcie {
 339                                 ralink,group = "pcie";
 340                                 ralink,function = "pcie rst";
 341                         };
 342                 };
 343
 344                 nand_pins: nand {
 345                         spi-nand {
 346                                 ralink,group = "spi";
 347                                 ralink,function = "nand1";
 348                         };
 349
 350                         sdhci-nand {
 351                                 ralink,group = "sdhci";
 352                                 ralink,function = "nand2";
 353                         };
 354                 };
 355
 356                 sdhci_pins: sdhci {
 357                         sdhci {
 358                                 ralink,group = "sdhci";
 359                                 ralink,function = "sdhci";
 360                         };
 361                 };
 362         };
 363
 364         rstctrl: rstctrl {
 365                 compatible = "ralink,rt2880-reset";
 366                 #reset-cells = <1>;
 367         };
 368
 369         clkctrl: clkctrl {
 370                 compatible = "ralink,rt2880-clock";
 371                 #clock-cells = <1>;
 372         };
 373
 374         sdhci: sdhci@1E130000 {
 375                 status = "disabled";
 376
 377                 compatible = "ralink,mt7620-sdhci";
 378                 reg = <0x1E130000 0x4000>;
 379
 380                 interrupt-parent = <&gic>;
 381                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 382
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&sdhci_pins>;
 385         };
 386
 387         xhci: xhci@1E1C0000 {
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 status = "okay";
 391
 392                 compatible = "mediatek,mt8173-xhci";
 393                 reg = <0x1e1c0000 0x1000
 394                        0x1e1d0700 0x0100>;
 395                 reg-names = "mac", "ippc";
 396
 397                 clocks = <&sysclock>;
 398                 clock-names = "sys_ck";
 399
 400                 interrupt-parent = <&gic>;
 401                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 402
 403                 /*
 404                  * Port 1 of both hubs is one usb slot and referenced here.
 405                  * The binding doesn't allow to address individual hubs.
 406                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 407                  */
 408                 xhci_ehci_port1: port@1 {
 409                         reg = <1>;
 410                         #trigger-source-cells = <0>;
 411                 };
 412
 413                 /*
 414                  * Only the second usb hub has a second port. That port serves
 415                  * ehci and ohci.
 416                  */
 417                 ehci_port2: port@2 {
 418                         reg = <2>;
 419                         #trigger-source-cells = <0>;
 420                 };
 421         };
 422
 423         gic: interrupt-controller@1fbc0000 {
 424                 compatible = "mti,gic";
 425                 reg = <0x1fbc0000 0x2000>;
 426
 427                 interrupt-controller;
 428                 #interrupt-cells = <3>;
 429
 430                 mti,reserved-cpu-vectors = <7>;
 431
 432                 timer {
 433                         compatible = "mti,gic-timer";
 434                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 435                         clocks = <&pll MT7621_CLK_CPU>;
 436                 };
 437         };
 438
 439         nand: nand@1e003000 {
 440                 status = "disabled";
 441
 442                 compatible = "mtk,mt7621-nand";
 443                 bank-width = <2>;
 444                 reg = <0x1e003000 0x800
 445                         0x1e003800 0x800>;
 446         };
 447
 448         ethernet: ethernet@1e100000 {
 449                 compatible = "mediatek,mt7621-eth";
 450                 reg = <0x1e100000 0x10000>;
 451
 452                 #address-cells = <1>;
 453                 #size-cells = <1>;
 454
 455                 resets = <&rstctrl 6 &rstctrl 23>;
 456                 reset-names = "fe", "eth";
 457
 458                 interrupt-parent = <&gic>;
 459                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 460
 461                 mediatek,switch = <&gsw>;
 462
 463                 mdio-bus {
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466
 467                         phy1f: ethernet-phy@1f {
 468                                 reg = <0x1f>;
 469                                 phy-mode = "rgmii";
 470                         };
 471                 };
 472
 473                 hnat: hnat@0 {
 474                         compatible = "mediatek,mt7623-hnat";
 475                         reg = <0 0x10000>;
 476                         mtketh-ppd = "eth0";
 477                         mtketh-lan = "eth0";
 478                         mtketh-wan = "eth0";
 479                         resets = <&rstctrl 0>;
 480                         reset-names = "mtketh";
 481                 };
 482         };
 483
 484         gsw: gsw@1e110000 {
 485                 compatible = "mediatek,mt7621-gsw";
 486                 reg = <0x1e110000 0x8000>;
 487                 interrupt-parent = <&gic>;
 488                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 489         };
 490
 491         pcie: pcie@1e140000 {
 492                 compatible = "mediatek,mt7621-pci";
 493                 reg = <0x1e140000 0x100
 494                         0x1e142000 0x100>;
 495
 496                 #address-cells = <3>;
 497                 #size-cells = <2>;
 498
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&pcie_pins>;
 501
 502                 device_type = "pci";
 503
 504                 bus-range = <0 255>;
 505                 ranges = <
 506                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 507                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 508                 >;
 509
 510                 interrupt-parent = <&gic>;
 511                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 512                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 513                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 514
 515                 status = "disabled";
 516
 517                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 518                 reset-names = "pcie0", "pcie1", "pcie2";
 519                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 520                 clock-names = "pcie0", "pcie1", "pcie2";
 521
 522                 pcie0: pcie@0,0 {
 523                         reg = <0x0000 0 0 0 0>;
 524
 525                         #address-cells = <3>;
 526                         #size-cells = <2>;
 527
 528                         ranges;
 529                 };
 530
 531                 pcie1: pcie@1,0 {
 532                         reg = <0x0800 0 0 0 0>;
 533
 534                         #address-cells = <3>;
 535                         #size-cells = <2>;
 536
 537                         ranges;
 538                 };
 539
 540                 pcie2: pcie@2,0 {
 541                         reg = <0x1000 0 0 0 0>;
 542
 543                         #address-cells = <3>;
 544                         #size-cells = <2>;
 545
 546                         ranges;
 547                 };
 548         };
 549 };