target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/clock/mt7621-clk.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "mediatek,mt7621-soc";
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "mips,mips1004Kc";
  16                         reg = <0x0>;
  17                 };
  18
  19                 cpu@1 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips1004Kc";
  22                         reg = <0x1>;
  23                 };
  24         };
  25
  26         cpuintc: cpuintc {
  27                 #address-cells = <0>;
  28                 #interrupt-cells = <1>;
  29                 interrupt-controller;
  30                 compatible = "mti,cpu-interrupt-controller";
  31         };
  32
  33         aliases {
  34                 serial0 = &uartlite;
  35         };
  36
  37         clkxtal: clkxtal {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 clock-frequency = <40000000>;
  41                 clock-output-names = "clkxtal";
  42         };
  43
  44         cpuclock: cpuclock {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47
  48                 /* FIXME: there should be way to detect this */
  49                 clock-frequency = <880000000>;
  50         };
  51
  52         sysclock: sysclock {
  53                 #clock-cells = <0>;
  54                 compatible = "fixed-clock";
  55
  56                 /* FIXME: there should be way to detect this */
  57                 clock-frequency = <50000000>;
  58         };
  59
  60
  61
  62         palmbus: palmbus@1E000000 {
  63                 compatible = "palmbus";
  64                 reg = <0x1E000000 0x100000>;
  65                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  66
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69
  70                 sysc: sysc@0 {
  71                         compatible = "mtk,mt7621-sysc";
  72                         reg = <0x0 0x100>;
  73                 };
  74
  75                 wdt: wdt@100 {
  76                         compatible = "mediatek,mt7621-wdt";
  77                         reg = <0x100 0x100>;
  78                 };
  79
  80                 gpio@600 {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83
  84                         compatible = "mtk,mt7621-gpio";
  85                         reg = <0x600 0x100>;
  86
  87                         gpio0: bank@0 {
  88                                 reg = <0>;
  89                                 compatible = "mtk,mt7621-gpio-bank";
  90                                 gpio-controller;
  91                                 #gpio-cells = <2>;
  92                         };
  93
  94                         gpio1: bank@1 {
  95                                 reg = <1>;
  96                                 compatible = "mtk,mt7621-gpio-bank";
  97                                 gpio-controller;
  98                                 #gpio-cells = <2>;
  99                         };
 100
 101                         gpio2: bank@2 {
 102                                 reg = <2>;
 103                                 compatible = "mtk,mt7621-gpio-bank";
 104                                 gpio-controller;
 105                                 #gpio-cells = <2>;
 106                         };
 107                 };
 108
 109                 i2c: i2c@900 {
 110                         compatible = "mediatek,mt7621-i2c";
 111                         reg = <0x900 0x100>;
 112
 113                         clocks = <&sysclock>;
 114
 115                         resets = <&rstctrl 16>;
 116                         reset-names = "i2c";
 117
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120
 121                         status = "disabled";
 122
 123                         pinctrl-names = "default";
 124                         pinctrl-0 = <&i2c_pins>;
 125                 };
 126
 127                 i2s: i2s@a00 {
 128                         compatible = "mediatek,mt7621-i2s";
 129                         reg = <0xa00 0x100>;
 130
 131                         clocks = <&sysclock>;
 132
 133                         resets = <&rstctrl 17>;
 134                         reset-names = "i2s";
 135
 136                         interrupt-parent = <&gic>;
 137                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 138
 139                         txdma-req = <2>;
 140                         rxdma-req = <3>;
 141
 142                         dmas = <&gdma 4>,
 143                                 <&gdma 6>;
 144                         dma-names = "tx", "rx";
 145
 146                         status = "disabled";
 147                 };
 148
 149                 systick: systick@d00 {
 150                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 151                         reg = <0xd00 0x10>;
 152
 153                         resets = <&rstctrl 28>;
 154                         reset-names = "intc";
 155
 156                         interrupt-parent = <&gic>;
 157                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 158                 };
 159
 160                 memc: memc@5000 {
 161                         compatible = "mtk,mt7621-memc";
 162                         reg = <0x300 0x100>;
 163                 };
 164
 165                 cpc: cpc@1fbf0000 {
 166                              compatible = "mtk,mt7621-cpc";
 167                              reg = <0x1fbf0000 0x8000>;
 168                 };
 169
 170                 mc: mc@1fbf8000 {
 171                             compatible = "mtk,mt7621-mc";
 172                             reg = <0x1fbf8000 0x8000>;
 173                 };
 174
 175                 uartlite: uartlite@c00 {
 176                         compatible = "ns16550a";
 177                         reg = <0xc00 0x100>;
 178
 179                         clocks = <&sysclock>;
 180                         clock-frequency = <50000000>;
 181
 182                         interrupt-parent = <&gic>;
 183                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                         reg-shift = <2>;
 186                         reg-io-width = <4>;
 187                         no-loopback-test;
 188                 };
 189
 190                 spi0: spi@b00 {
 191                         status = "disabled";
 192
 193                         compatible = "ralink,mt7621-spi";
 194                         reg = <0xb00 0x100>;
 195
 196                         clocks = <&sysclock>;
 197
 198                         resets = <&rstctrl 18>;
 199                         reset-names = "spi";
 200
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203
 204                         pinctrl-names = "default";
 205                         pinctrl-0 = <&spi_pins>;
 206                 };
 207
 208                 gdma: gdma@2800 {
 209                         compatible = "ralink,rt3883-gdma";
 210                         reg = <0x2800 0x800>;
 211
 212                         resets = <&rstctrl 14>;
 213                         reset-names = "dma";
 214
 215                         interrupt-parent = <&gic>;
 216                         interrupts = <0 13 4>;
 217
 218                         #dma-cells = <1>;
 219                         #dma-channels = <16>;
 220                         #dma-requests = <16>;
 221
 222                         status = "disabled";
 223                 };
 224
 225                 hsdma: hsdma@7000 {
 226                         compatible = "mediatek,mt7621-hsdma";
 227                         reg = <0x7000 0x1000>;
 228
 229                         resets = <&rstctrl 5>;
 230                         reset-names = "hsdma";
 231
 232                         interrupt-parent = <&gic>;
 233                         interrupts = <0 11 4>;
 234
 235                         #dma-cells = <1>;
 236                         #dma-channels = <1>;
 237                         #dma-requests = <1>;
 238
 239                         status = "disabled";
 240                 };
 241         };
 242
 243         pinctrl: pinctrl {
 244                 compatible = "ralink,rt2880-pinmux";
 245                 pinctrl-names = "default";
 246                 pinctrl-0 = <&state_default>;
 247
 248                 state_default: pinctrl0 {
 249                 };
 250
 251                 i2c_pins: i2c {
 252                         i2c {
 253                                 ralink,group = "i2c";
 254                                 ralink,function = "i2c";
 255                         };
 256                 };
 257
 258                 spi_pins: spi {
 259                         spi {
 260                                 ralink,group = "spi";
 261                                 ralink,function = "spi";
 262                         };
 263                 };
 264
 265                 uart1_pins: uart1 {
 266                         uart1 {
 267                                 ralink,group = "uart1";
 268                                 ralink,function = "uart1";
 269                         };
 270                 };
 271
 272                 uart2_pins: uart2 {
 273                         uart2 {
 274                                 ralink,group = "uart2";
 275                                 ralink,function = "uart2";
 276                         };
 277                 };
 278
 279                 uart3_pins: uart3 {
 280                         uart3 {
 281                                 ralink,group = "uart3";
 282                                 ralink,function = "uart3";
 283                         };
 284                 };
 285
 286                 rgmii1_pins: rgmii1 {
 287                         rgmii1 {
 288                                 ralink,group = "rgmii1";
 289                                 ralink,function = "rgmii1";
 290                         };
 291                 };
 292
 293                 rgmii2_pins: rgmii2 {
 294                         rgmii2 {
 295                                 ralink,group = "rgmii2";
 296                                 ralink,function = "rgmii2";
 297                         };
 298                 };
 299
 300                 mdio_pins: mdio {
 301                         mdio {
 302                                 ralink,group = "mdio";
 303                                 ralink,function = "mdio";
 304                         };
 305                 };
 306
 307                 pcie_pins: pcie {
 308                         pcie {
 309                                 ralink,group = "pcie";
 310                                 ralink,function = "pcie rst";
 311                         };
 312                 };
 313
 314                 nand_pins: nand {
 315                         spi-nand {
 316                                 ralink,group = "spi";
 317                                 ralink,function = "nand1";
 318                         };
 319
 320                         sdhci-nand {
 321                                 ralink,group = "sdhci";
 322                                 ralink,function = "nand2";
 323                         };
 324                 };
 325
 326                 sdhci_pins: sdhci {
 327                         sdhci {
 328                                 ralink,group = "sdhci";
 329                                 ralink,function = "sdhci";
 330                         };
 331                 };
 332         };
 333
 334         rstctrl: rstctrl {
 335                 compatible = "ralink,rt2880-reset";
 336                 #reset-cells = <1>;
 337         };
 338
 339         clkctrl: clkctrl {
 340                 compatible = "ralink,rt2880-clock";
 341                 #clock-cells = <1>;
 342         };
 343
 344         sdhci: sdhci@1E130000 {
 345                 status = "disabled";
 346
 347                 compatible = "ralink,mt7620-sdhci";
 348                 reg = <0x1E130000 0x4000>;
 349
 350                 interrupt-parent = <&gic>;
 351                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 352         };
 353
 354         xhci: xhci@1E1C0000 {
 355                 status = "okay";
 356
 357                 compatible = "mediatek,mt8173-xhci";
 358                 reg = <0x1e1c0000 0x1000
 359                        0x1e1d0700 0x0100>;
 360                 reg-names = "mac", "ippc";
 361
 362                 clocks = <&sysclock>;
 363                 clock-names = "sys_ck";
 364
 365                 interrupt-parent = <&gic>;
 366                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 367         };
 368
 369         gic: interrupt-controller@1fbc0000 {
 370                 compatible = "mti,gic";
 371                 reg = <0x1fbc0000 0x2000>;
 372
 373                 interrupt-controller;
 374                 #interrupt-cells = <3>;
 375
 376                 mti,reserved-cpu-vectors = <7>;
 377
 378                 timer {
 379                         compatible = "mti,gic-timer";
 380                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 381                         clocks = <&cpuclock>;
 382                 };
 383         };
 384
 385         nand: nand@1e003000 {
 386                 status = "disabled";
 387
 388                 compatible = "mtk,mt7621-nand";
 389                 bank-width = <2>;
 390                 reg = <0x1e003000 0x800
 391                         0x1e003800 0x800>;
 392                 #address-cells = <1>;
 393                 #size-cells = <1>;
 394         };
 395
 396         ethsys: syscon@1e000000 {
 397                 compatible = "mediatek,mt7621-ethsys",
 398                              "syscon";
 399                 reg = <0x1e000000 0x100>;
 400                 #clock-cells = <1>;
 401                 #reset-cells = <1>;
 402         };
 403
 404         eth: ethernet@1e100000 {
 405                 compatible = "mediatek,mt7621-eth",
 406                              "syscon";
 407                 reg = <0x1e100000 0xe000>;
 408                 interrupt-parent = <&gic>;
 409                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 410                 clocks = <&ethsys CLK_ETHSYS_ETH>,
 411                          <&ethsys CLK_ETHSYS_ESW>;
 412                 clock-names = "ethif", "esw";
 413                 resets = <&rstctrl 6>,
 414                          <&rstctrl 23>,
 415                          <&rstctrl 0>;
 416                 reset-names = "fe", "gmac", "ppe";
 417                 mediatek,ethsys = <&ethsys>;
 418                 mediatek,pctl = <&ethsys>;
 419                 status = "disabled";
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422         };
 423
 424         pcie: pcie@1e140000 {
 425                 compatible = "mediatek,mt7621-pci";
 426                 reg = <0x1e140000 0x100
 427                         0x1e142000 0x100>;
 428
 429                 #address-cells = <3>;
 430                 #size-cells = <2>;
 431
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&pcie_pins>;
 434
 435                 device_type = "pci";
 436
 437                 bus-range = <0 255>;
 438                 ranges = <
 439                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 440                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 441                 >;
 442
 443                 interrupt-parent = <&gic>;
 444                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 445                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 446                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 447
 448                 status = "disabled";
 449
 450                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 451                 reset-names = "pcie0", "pcie1", "pcie2";
 452                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 453                 clock-names = "pcie0", "pcie1", "pcie2";
 454
 455                 pcie0 {
 456                         reg = <0x0000 0 0 0 0>;
 457
 458                         #address-cells = <3>;
 459                         #size-cells = <2>;
 460                 };
 461
 462                 pcie1 {
 463                         reg = <0x0800 0 0 0 0>;
 464
 465                         #address-cells = <3>;
 466                         #size-cells = <2>;
 467                 };
 468
 469                 pcie2 {
 470                         reg = <0x1000 0 0 0 0>;
 471
 472                         #address-cells = <3>;
 473                         #size-cells = <2>;
 474                 };
 475         };
 476 };