ramips: convert rt2x00 EEPROM to NVMEM format
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7620a_tplink_archer-c2-v1.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc";
8 model = "TP-Link Archer C2 v1";
9
10 aliases {
11 led-boot = &led_wps;
12 led-failsafe = &led_wps;
13 led-running = &led_wps;
14 led-upgrade = &led_wps;
15 };
16
17 chosen {
18 bootargs = "console=ttyS0,115200";
19 };
20
21 leds {
22 compatible = "gpio-leds";
23
24 lan {
25 label = "green:lan";
26 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
27 };
28
29 usb {
30 label = "green:usb";
31 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
32 trigger-sources = <&ohci_port1>, <&ehci_port1>;
33 linux,default-trigger = "usbport";
34 };
35
36 led_wps: wps {
37 label = "green:wps";
38 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
39 };
40
41 wan {
42 label = "green:wan";
43 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
44 };
45
46 wlan {
47 label = "green:wlan";
48 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
49 linux,default-trigger = "phy1tpt";
50 };
51 };
52
53 keys {
54 compatible = "gpio-keys";
55
56 reset_wps {
57 label = "reset_wps";
58 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_RESTART>;
60 };
61
62 rfkill {
63 label = "rfkill";
64 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
65 linux,code = <KEY_RFKILL>;
66 };
67 };
68
69 rtl8367rb {
70 compatible = "realtek,rtl8367b", "rtl8367b";
71 cpu_port = <6>;
72 realtek,extif1 = <1 0 1 1 1 1 1 1 2>;
73 mii-bus = <&mdio0>;
74 };
75 };
76
77 &spi0 {
78 status = "okay";
79
80 flash@0 {
81 compatible = "jedec,spi-nor";
82 reg = <0>;
83 spi-max-frequency = <30000000>;
84
85 partitions {
86 compatible = "fixed-partitions";
87 #address-cells = <1>;
88 #size-cells = <1>;
89
90 partition@0 {
91 label = "u-boot";
92 reg = <0x0 0x20000>;
93 read-only;
94 };
95
96 partition@20000 {
97 compatible = "tplink,firmware";
98 label = "firmware";
99 reg = <0x20000 0x7a0000>;
100 };
101
102 partition@7c0000 {
103 label = "config";
104 reg = <0x7c0000 0x10000>;
105 read-only;
106 };
107
108 rom: partition@7d0000 {
109 compatible = "nvmem-cells";
110 label = "rom";
111 reg = <0x7d0000 0x10000>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 read-only;
115
116 macaddr_rom_f100: macaddr@f100 {
117 reg = <0xf100 0x6>;
118 };
119 };
120
121 partition@7e0000 {
122 label = "romfile";
123 reg = <0x7e0000 0x10000>;
124 read-only;
125 };
126
127 radio: partition@7f0000 {
128 compatible = "nvmem-cells";
129 label = "radio";
130 reg = <0x7f0000 0x10000>;
131 #address-cells = <1>;
132 #size-cells = <1>;
133 read-only;
134
135 eeprom_radio_0: eeprom@0 {
136 reg = <0x0 0x200>;
137 };
138 };
139 };
140 };
141 };
142
143 &ethernet {
144 pinctrl-names = "default";
145 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
146
147 nvmem-cells = <&macaddr_rom_f100>;
148 nvmem-cell-names = "mac-address";
149
150 port@5 {
151 status = "okay";
152 mediatek,fixed-link = <1000 1 1 1>;
153 phy-mode = "rgmii";
154 };
155
156 mdio0: mdio-bus {
157 status = "okay";
158 };
159 };
160
161 &gpio1 {
162 status = "okay";
163 };
164
165 &gpio2 {
166 status = "okay";
167 };
168
169 &gpio3 {
170 status = "okay";
171 };
172
173 &state_default {
174 gpio {
175 groups = "i2c", "uartf", "wled", "ephy", "spi refclk";
176 function = "gpio";
177 };
178 };
179
180 &wmac {
181 nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100>;
182 nvmem-cell-names = "eeprom", "mac-address";
183 };
184
185 &ehci {
186 status = "okay";
187 };
188
189 &ohci {
190 status = "okay";
191 };
192
193 &pcie {
194 status = "okay";
195 };
196
197 &pcie0 {
198 mt76@0,0 {
199 reg = <0x0000 0 0 0 0>;
200 mediatek,mtd-eeprom = <&radio 0x8000>;
201 nvmem-cells = <&macaddr_rom_f100>;
202 nvmem-cell-names = "mac-address";
203 mac-address-increment = <(-1)>;
204 };
205 };