target/linux/ramips/dts/mt7620a_phicomm_psg1208.dts

   1 #include "mt7620a.dtsi"
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         compatible = "phicomm,psg1208", "ralink,mt7620a-soc";
   8         model = "Phicomm PSG1208";
   9
  10         aliases {
  11                 led-boot = &led_wps;
  12                 led-failsafe = &led_wps;
  13                 led-running = &led_wps;
  14                 led-upgrade = &led_wps;
  15         };
  16
  17         leds {
  18                 compatible = "gpio-leds";
  19
  20                 led_wps: wps {
  21                         label = "white:wps";
  22                         gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  23                 };
  24
  25                 wlan {
  26                         label = "white:wlan2g";
  27                         gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  28                 };
  29         };
  30
  31         keys {
  32                 compatible = "gpio-keys";
  33
  34                 reset {
  35                         label = "reset";
  36                         gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_RESTART>;
  38                 };
  39         };
  40 };
  41
  42 &gpio1 {
  43         status = "okay";
  44 };
  45
  46 &gpio3 {
  47         status = "okay";
  48 };
  49
  50 &spi0 {
  51         status = "okay";
  52
  53         flash@0 {
  54                 compatible = "jedec,spi-nor";
  55                 reg = <0>;
  56                 spi-max-frequency = <80000000>;
  57                 m25p,fast-read;
  58
  59                 partitions {
  60                         compatible = "fixed-partitions";
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63
  64                         partition@0 {
  65                                 label = "u-boot";
  66                                 reg = <0x0 0x30000>;
  67                                 read-only;
  68                         };
  69
  70                         partition@30000 {
  71                                 label = "u-boot-env";
  72                                 reg = <0x30000 0x10000>;
  73                                 read-only;
  74                         };
  75
  76                         factory: partition@40000 {
  77                                 compatible = "nvmem-cells";
  78                                 label = "factory";
  79                                 reg = <0x40000 0x10000>;
  80                                 #address-cells = <1>;
  81                                 #size-cells = <1>;
  82                                 read-only;
  83
  84                                 eeprom_factory_0: eeprom@0 {
  85                                         reg = <0x0 0x200>;
  86                                 };
  87
  88                                 eeprom_factory_8000: eeprom@8000 {
  89                                         reg = <0x8000 0x200>;
  90                                 };
  91
  92                                 macaddr_factory_4: macaddr@4 {
  93                                         reg = <0x4 0x6>;
  94                                 };
  95                         };
  96
  97                         partition@50000 {
  98                                 compatible = "denx,uimage";
  99                                 label = "firmware";
 100                                 reg = <0x50000 0x7b0000>;
 101                         };
 102                 };
 103         };
 104 };
 105
 106 &state_default {
 107         gpio {
 108                 groups = "i2c", "spi refclk", "wled";
 109                 function = "gpio";
 110         };
 111 };
 112
 113 &ethernet {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&ephy_pins>;
 116
 117         nvmem-cells = <&macaddr_factory_4>;
 118         nvmem-cell-names = "mac-address";
 119
 120         mediatek,portmap = "llllw";
 121 };
 122
 123 &pcie {
 124         status = "okay";
 125 };
 126
 127 &pcie0 {
 128         mt76@0,0 {
 129                 reg = <0x0000 0 0 0 0>;
 130                 nvmem-cells = <&eeprom_factory_8000>;
 131                 nvmem-cell-names = "eeprom";
 132                 ieee80211-freq-limit = <5000000 6000000>;
 133         };
 134 };
 135
 136 &wmac {
 137         nvmem-cells = <&eeprom_factory_0>;
 138         nvmem-cell-names = "eeprom";
 139 };