target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         compatible = "lb-link,bl-w1200", "ralink,mt7620a-soc";
  10         model = "LB-Link BL-W1200";
  11
  12         aliases {
  13                 led-boot = &led_wps;
  14                 led-failsafe = &led_wps;
  15                 led-upgrade = &led_wps;
  16         };
  17
  18         keys {
  19                 compatible = "gpio-keys";
  20
  21                 reset_wps {
  22                         label = "reset_wps";
  23                         gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  24                         linux,code = <KEY_RESTART>;
  25                 };
  26         };
  27
  28         leds {
  29                 compatible = "gpio-leds";
  30
  31                 led_wps: wps {
  32                         label = "green:wps";
  33                         gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  34                 };
  35         };
  36 };
  37
  38 &gpio1 {
  39         status = "okay";
  40 };
  41
  42 &spi0 {
  43         status = "okay";
  44
  45         flash@0 {
  46                 compatible = "jedec,spi-nor";
  47                 reg = <0>;
  48                 spi-max-frequency = <50000000>;
  49
  50                 partitions {
  51                         compatible = "fixed-partitions";
  52                         #address-cells = <1>;
  53                         #size-cells = <1>;
  54
  55                         partition@0 {
  56                                 label = "u-boot";
  57                                 reg = <0x0 0x30000>;
  58                                 read-only;
  59                         };
  60
  61                         partition@30000 {
  62                                 label = "config";
  63                                 reg = <0x30000 0x10000>;
  64                                 read-only;
  65                         };
  66
  67                         factory: partition@40000 {
  68                                 compatible = "nvmem-cells";
  69                                 label = "factory";
  70                                 reg = <0x40000 0x10000>;
  71                                 #address-cells = <1>;
  72                                 #size-cells = <1>;
  73                                 read-only;
  74
  75                                 eeprom_factory_0: eeprom@0 {
  76                                         reg = <0x0 0x200>;
  77                                 };
  78
  79                                 macaddr_factory_28: macaddr@28 {
  80                                         reg = <0x28 0x6>;
  81                                 };
  82                         };
  83
  84                         partition@50000 {
  85                                 compatible = "denx,uimage";
  86                                 label = "firmware";
  87                                 reg = <0x50000 0x7b0000>;
  88                         };
  89                 };
  90         };
  91 };
  92
  93 &state_default {
  94         gpio {
  95                 groups = "uartf", "spi refclk";
  96                 function = "gpio";
  97         };
  98 };
  99
 100 &ethernet {
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&rgmii2_pins &mdio_pins>;
 103
 104         nvmem-cells = <&macaddr_factory_28>;
 105         nvmem-cell-names = "mac-address";
 106
 107         mediatek,portmap = "wllll";
 108
 109         port@5 {
 110                 status = "okay";
 111                 mediatek,fixed-link = <1000 1 1 1>;
 112                 phy-mode = "rgmii";
 113         };
 114
 115         mdio-bus {
 116                 status = "okay";
 117
 118                 ethernet-phy@0 {
 119                         reg = <0>;
 120                         phy-mode = "rgmii";
 121                 };
 122
 123                 ethernet-phy@1 {
 124                         reg = <1>;
 125                         phy-mode = "rgmii";
 126                 };
 127
 128                 ethernet-phy@2 {
 129                         reg = <2>;
 130                         phy-mode = "rgmii";
 131                 };
 132
 133                 ethernet-phy@3 {
 134                         reg = <3>;
 135                         phy-mode = "rgmii";
 136                 };
 137
 138                 ethernet-phy@4 {
 139                         reg = <4>;
 140                         phy-mode = "rgmii";
 141                 };
 142
 143                 ethernet-phy@1f {
 144                         reg = <0x1f>;
 145                         phy-mode = "rgmii";
 146                 };
 147         };
 148 };
 149
 150 &gsw {
 151         mediatek,ephy-base = /bits/ 8 <12>;
 152 };
 153
 154 &wmac {
 155         nvmem-cells = <&eeprom_factory_0>;
 156         nvmem-cell-names = "eeprom";
 157 };
 158
 159 &pcie {
 160         status = "okay";
 161 };
 162
 163 &pcie0 {
 164         wifi@0,0 {
 165                 compatible = "mediatek,mt76";
 166                 reg = <0x0000 0 0 0 0>;
 167                 ieee80211-freq-limit = <5000000 6000000>;
 168                 mediatek,mtd-eeprom = <&factory 0x8000>;
 169
 170                 led {
 171                         led-sources = <2>;
 172                         led-active-low;
 173                 };
 174         };
 175 };
 176
 177 &ehci {
 178         status = "okay";
 179 };
 180
 181 &ohci {
 182         status = "okay";
 183 };