ramips: convert mt76 PCIe NIC EEPROM to NVMEM format for legacy SoCs
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7620a_edimax_ew-747x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
8
9 / {
10 compatible = "ralink,mt7620a-soc";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 keys {
20 compatible = "gpio-keys";
21
22 reset_wps {
23 label = "reset_wps";
24 gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
25 linux,code = <KEY_RESTART>;
26 };
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 led_power: power {
33 label = "green:power";
34 gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
35 };
36
37 lan {
38 label = "green:lan";
39 gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
40 };
41
42 wps {
43 label = "green:wps";
44 gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
45 };
46 };
47 };
48
49 &gpio1 {
50 status = "okay";
51 };
52
53 &gpio2 {
54 status = "okay";
55 };
56
57 &spi0 {
58 status = "okay";
59
60 flash@0 {
61 compatible = "jedec,spi-nor";
62 reg = <0>;
63 spi-max-frequency = <10000000>;
64
65 partitions {
66 compatible = "fixed-partitions";
67 #address-cells = <1>;
68 #size-cells = <1>;
69
70 partition@0 {
71 label = "u-boot";
72 reg = <0x0 0x30000>;
73 read-only;
74 };
75
76 partition@30000 {
77 label = "u-boot-env";
78 reg = <0x30000 0x10000>;
79 read-only;
80 };
81
82 factory: partition@40000 {
83 compatible = "nvmem-cells";
84 label = "factory";
85 reg = <0x40000 0x10000>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 read-only;
89
90 eeprom_factory_0: eeprom@0 {
91 reg = <0x0 0x200>;
92 };
93
94 eeprom_factory_8000: eeprom@8000 {
95 reg = <0x8000 0x200>;
96 };
97
98 macaddr_factory_4: macaddr@4 {
99 reg = <0x4 0x6>;
100 };
101 };
102
103 partition@50000 {
104 label = "cimage";
105 reg = <0x50000 0x20000>;
106 read-only;
107 };
108
109 partition@70000 {
110 compatible = "openwrt,uimage", "denx,uimage";
111 openwrt,offset = <FW_EDIMAX_OFFSET>;
112 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
113 label = "firmware";
114 reg = <0x00070000 0x00790000>;
115 };
116 };
117 };
118 };
119
120 &state_default {
121 gpio {
122 groups = "i2c", "uartf", "nd_sd", "rgmii2";
123 function = "gpio";
124 };
125 };
126
127 &pinctrl {
128 phy_reset_pins: phy-reset {
129 gpio {
130 groups = "spi refclk";
131 function = "gpio";
132 };
133 };
134 };
135
136 &ethernet {
137 pinctrl-names = "default";
138 pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
139
140 nvmem-cells = <&macaddr_factory_4>;
141 nvmem-cell-names = "mac-address";
142
143 phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
144 phy-reset-duration = <30>;
145
146 port@5 {
147 status = "okay";
148 mediatek,fixed-link = <1000 1 1 1>;
149 phy-mode = "rgmii";
150 };
151
152 mdio-bus {
153 status = "okay";
154
155 phy0: ethernet-phy@0 {
156 status = "disabled";
157 reg = <0>;
158 phy-mode = "rgmii";
159 };
160
161 phy1: ethernet-phy@1 {
162 status = "disabled";
163 reg = <1>;
164 phy-mode = "rgmii";
165 };
166
167 phy2: ethernet-phy@2 {
168 status = "disabled";
169 reg = <2>;
170 phy-mode = "rgmii";
171 };
172
173 phy3: ethernet-phy@3 {
174 status = "disabled";
175 reg = <3>;
176 phy-mode = "rgmii";
177 };
178
179 phy4: ethernet-phy@4 {
180 status = "disabled";
181 reg = <4>;
182 phy-mode = "rgmii";
183 };
184 };
185 };
186
187 &gsw {
188 mediatek,ephy-base = /bits/ 8 <8>;
189 };
190
191 &wmac {
192 nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_4>;
193 nvmem-cell-names = "eeprom", "mac-address";
194 };
195
196 &pcie {
197 status = "okay";
198 };
199
200 &pcie0 {
201 wifi@0,0 {
202 reg = <0x0000 0 0 0 0>;
203 ieee80211-freq-limit = <5000000 6000000>;
204 nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_4>;
205 nvmem-cell-names = "eeprom", "mac-address";
206 mac-address-increment = <2>;
207 };
208 };