target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7 #include <dt-bindings/mtd/partitions/uimage.h>
   8
   9 / {
  10         compatible = "ralink,mt7620a-soc";
  11
  12         aliases {
  13                 led-boot = &led_power;
  14                 led-failsafe = &led_power;
  15                 led-running = &led_power;
  16                 led-upgrade = &led_power;
  17         };
  18
  19         keys {
  20                 compatible = "gpio-keys";
  21
  22                 reset_wps {
  23                         label = "reset_wps";
  24                         gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
  25                         linux,code = <KEY_RESTART>;
  26                 };
  27         };
  28
  29         leds {
  30                 compatible = "gpio-leds";
  31
  32                 led_power: power {
  33                         label = "green:power";
  34                         gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
  35                 };
  36
  37                 lan {
  38                         label = "green:lan";
  39                         gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
  40                 };
  41
  42                 wps {
  43                         label = "green:wps";
  44                         gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
  45                 };
  46         };
  47 };
  48
  49 &gpio1 {
  50         status = "okay";
  51 };
  52
  53 &gpio2 {
  54         status = "okay";
  55 };
  56
  57 &spi0 {
  58         status = "okay";
  59
  60         flash@0 {
  61                 compatible = "jedec,spi-nor";
  62                 reg = <0>;
  63                 spi-max-frequency = <10000000>;
  64
  65                 partitions {
  66                         compatible = "fixed-partitions";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69
  70                         partition@0 {
  71                                 label = "u-boot";
  72                                 reg = <0x0 0x30000>;
  73                                 read-only;
  74                         };
  75
  76                         partition@30000 {
  77                                 label = "u-boot-env";
  78                                 reg = <0x30000 0x10000>;
  79                                 read-only;
  80                         };
  81
  82                         factory: partition@40000 {
  83                                 compatible = "nvmem-cells";
  84                                 label = "factory";
  85                                 reg = <0x40000 0x10000>;
  86                                 #address-cells = <1>;
  87                                 #size-cells = <1>;
  88                                 read-only;
  89
  90                                 eeprom_factory_0: eeprom@0 {
  91                                         reg = <0x0 0x200>;
  92                                 };
  93
  94                                 macaddr_factory_4: macaddr@4 {
  95                                         reg = <0x4 0x6>;
  96                                 };
  97                         };
  98
  99                         partition@50000 {
 100                                 label = "cimage";
 101                                 reg = <0x50000 0x20000>;
 102                                 read-only;
 103                         };
 104
 105                         partition@70000 {
 106                                 compatible = "openwrt,uimage", "denx,uimage";
 107                                 openwrt,offset = <FW_EDIMAX_OFFSET>;
 108                                 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
 109                                 label = "firmware";
 110                                 reg = <0x00070000 0x00790000>;
 111                         };
 112                 };
 113         };
 114 };
 115
 116 &state_default {
 117         gpio {
 118                 groups = "i2c", "uartf", "nd_sd", "rgmii2";
 119                 function = "gpio";
 120         };
 121 };
 122
 123 &pinctrl {
 124         phy_reset_pins: phy-reset {
 125                 gpio {
 126                         groups = "spi refclk";
 127                         function = "gpio";
 128                 };
 129         };
 130 };
 131
 132 &ethernet {
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
 135
 136         nvmem-cells = <&macaddr_factory_4>;
 137         nvmem-cell-names = "mac-address";
 138
 139         phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 140         phy-reset-duration = <30>;
 141
 142         port@5 {
 143                 status = "okay";
 144                 mediatek,fixed-link = <1000 1 1 1>;
 145                 phy-mode = "rgmii";
 146         };
 147
 148         mdio-bus {
 149                 status = "okay";
 150
 151                 phy0: ethernet-phy@0 {
 152                         status = "disabled";
 153                         reg = <0>;
 154                         phy-mode = "rgmii";
 155                 };
 156
 157                 phy1: ethernet-phy@1 {
 158                         status = "disabled";
 159                         reg = <1>;
 160                         phy-mode = "rgmii";
 161                 };
 162
 163                 phy2: ethernet-phy@2 {
 164                         status = "disabled";
 165                         reg = <2>;
 166                         phy-mode = "rgmii";
 167                 };
 168
 169                 phy3: ethernet-phy@3 {
 170                         status = "disabled";
 171                         reg = <3>;
 172                         phy-mode = "rgmii";
 173                 };
 174
 175                 phy4: ethernet-phy@4 {
 176                         status = "disabled";
 177                         reg = <4>;
 178                         phy-mode = "rgmii";
 179                 };
 180         };
 181 };
 182
 183 &gsw {
 184         mediatek,ephy-base = /bits/ 8 <8>;
 185 };
 186
 187 &wmac {
 188         nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_4>;
 189         nvmem-cell-names = "eeprom", "mac-address";
 190 };
 191
 192 &pcie {
 193         status = "okay";
 194 };
 195
 196 &pcie0 {
 197         wifi@0,0 {
 198                 reg = <0x0000 0 0 0 0>;
 199                 mediatek,mtd-eeprom = <&factory 0x8000>;
 200                 ieee80211-freq-limit = <5000000 6000000>;
 201                 nvmem-cells = <&macaddr_factory_4>;
 202                 nvmem-cell-names = "mac-address";
 203                 mac-address-increment = <2>;
 204         };
 205 };