1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "mt7620a.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
9 compatible = "ralink,mt7620a-soc";
12 led-boot = &led_power;
13 led-failsafe = &led_power;
14 led-running = &led_power;
15 led-upgrade = &led_power;
19 compatible = "gpio-keys";
23 gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
24 linux,code = <KEY_RESTART>;
28 label = "switch high";
29 gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
31 linux,input-type = <EV_SW>;
36 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
38 linux,input-type = <EV_SW>;
43 compatible = "gpio-leds";
46 label = "green:power";
47 gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
52 gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
56 label = "blue:wlan2g";
57 gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
58 linux,default-trigger = "phy1radio";
62 label = "blue:wlan5g";
63 gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
64 linux,default-trigger = "phy0radio";
69 gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
73 label = "green:crossband";
74 gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
91 compatible = "jedec,spi-nor";
93 spi-max-frequency = <10000000>;
96 compatible = "fixed-partitions";
107 label = "u-boot-env";
108 reg = <0x30000 0x10000>;
112 factory: partition@40000 {
114 reg = <0x40000 0x10000>;
120 reg = <0x50000 0x20000>;
125 compatible = "edimax,uimage";
127 reg = <0x00070000 0x00790000>;
135 groups = "i2c", "uartf", "nd_sd", "rgmii2";
141 phy_reset_pins: phy-reset {
143 groups = "spi refclk";
150 pinctrl-names = "default";
151 pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
153 mtd-mac-address = <&factory 0x4>;
155 mediatek,mdio-mode = <1>;
157 phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
158 phy-reset-duration = <30>;
162 mediatek,fixed-link = <1000 1 1 1>;
169 phy0: ethernet-phy@0 {
175 phy1: ethernet-phy@1 {
181 phy2: ethernet-phy@2 {
187 phy3: ethernet-phy@3 {
193 phy4: ethernet-phy@4 {
202 mediatek,port5 = "gmac";
206 ralink,mtd-eeprom = <&factory 0x0>;
215 reg = <0x0000 0 0 0 0>;
216 mediatek,mtd-eeprom = <&factory 0x8000>;