ramips: convert mtd-mac-address to nvmem implementation
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7620a_edimax_ew-747x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
8
9 / {
10 compatible = "ralink,mt7620a-soc";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 keys {
20 compatible = "gpio-keys";
21
22 reset_wps {
23 label = "reset_wps";
24 gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
25 linux,code = <KEY_RESTART>;
26 };
27
28 switch_high {
29 label = "switch high";
30 gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
31 linux,code = <BTN_0>;
32 linux,input-type = <EV_SW>;
33 };
34
35 switch_off {
36 label = "switch off";
37 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
38 linux,code = <BTN_1>;
39 linux,input-type = <EV_SW>;
40 };
41 };
42
43 leds {
44 compatible = "gpio-leds";
45
46 led_power: power {
47 label = "green:power";
48 gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
49 };
50
51 lan {
52 label = "green:lan";
53 gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
54 };
55
56 wlan2g {
57 label = "blue:wlan2g";
58 gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
59 linux,default-trigger = "phy1radio";
60 };
61
62 wlan5g {
63 label = "blue:wlan5g";
64 gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
65 linux,default-trigger = "phy0radio";
66 };
67
68 wps {
69 label = "green:wps";
70 gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
71 };
72
73 crossband {
74 label = "green:crossband";
75 gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
76 };
77 };
78 };
79
80 &gpio1 {
81 status = "okay";
82 };
83
84 &gpio2 {
85 status = "okay";
86 };
87
88 &spi0 {
89 status = "okay";
90
91 flash@0 {
92 compatible = "jedec,spi-nor";
93 reg = <0>;
94 spi-max-frequency = <10000000>;
95
96 partitions {
97 compatible = "fixed-partitions";
98 #address-cells = <1>;
99 #size-cells = <1>;
100
101 partition@0 {
102 label = "u-boot";
103 reg = <0x0 0x30000>;
104 read-only;
105 };
106
107 partition@30000 {
108 label = "u-boot-env";
109 reg = <0x30000 0x10000>;
110 read-only;
111 };
112
113 factory: partition@40000 {
114 label = "factory";
115 reg = <0x40000 0x10000>;
116 read-only;
117 };
118
119 partition@50000 {
120 label = "cimage";
121 reg = <0x50000 0x20000>;
122 read-only;
123 };
124
125 partition@70000 {
126 compatible = "openwrt,uimage", "denx,uimage";
127 openwrt,offset = <FW_EDIMAX_OFFSET>;
128 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
129 label = "firmware";
130 reg = <0x00070000 0x00790000>;
131 };
132 };
133 };
134 };
135
136 &state_default {
137 gpio {
138 groups = "i2c", "uartf", "nd_sd", "rgmii2";
139 function = "gpio";
140 };
141 };
142
143 &pinctrl {
144 phy_reset_pins: phy-reset {
145 gpio {
146 groups = "spi refclk";
147 function = "gpio";
148 };
149 };
150 };
151
152 &ethernet {
153 pinctrl-names = "default";
154 pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
155
156 nvmem-cells = <&macaddr_factory_4>;
157 nvmem-cell-names = "mac-address";
158
159 phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
160 phy-reset-duration = <30>;
161
162 port@5 {
163 status = "okay";
164 mediatek,fixed-link = <1000 1 1 1>;
165 phy-mode = "rgmii";
166 };
167
168 mdio-bus {
169 status = "okay";
170
171 phy0: ethernet-phy@0 {
172 status = "disabled";
173 reg = <0>;
174 phy-mode = "rgmii";
175 };
176
177 phy1: ethernet-phy@1 {
178 status = "disabled";
179 reg = <1>;
180 phy-mode = "rgmii";
181 };
182
183 phy2: ethernet-phy@2 {
184 status = "disabled";
185 reg = <2>;
186 phy-mode = "rgmii";
187 };
188
189 phy3: ethernet-phy@3 {
190 status = "disabled";
191 reg = <3>;
192 phy-mode = "rgmii";
193 };
194
195 phy4: ethernet-phy@4 {
196 status = "disabled";
197 reg = <4>;
198 phy-mode = "rgmii";
199 };
200 };
201 };
202
203 &gsw {
204 mediatek,ephy-base = /bits/ 8 <8>;
205 };
206
207 &wmac {
208 ralink,mtd-eeprom = <&factory 0x0>;
209 };
210
211 &pcie {
212 status = "okay";
213 };
214
215 &pcie0 {
216 wifi@0,0 {
217 reg = <0x0000 0 0 0 0>;
218 mediatek,mtd-eeprom = <&factory 0x8000>;
219 mediatek,2ghz = <0>;
220 };
221 };
222
223 &factory {
224 compatible = "nvmem-cells";
225 #address-cells = <1>;
226 #size-cells = <1>;
227
228 macaddr_factory_4: macaddr@4 {
229 reg = <0x4 0x6>;
230 };
231 };