ramips: convert rt2x00 EEPROM to NVMEM format
[openwrt/staging/stintel.git] / target / linux / ramips / dts / mt7620a_edimax_ew-7478apc.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
8
9 / {
10 compatible = "edimax,ew-7478apc", "ralink,mt7620a-soc";
11 model = "Edimax EW-7478APC";
12
13 aliases {
14 led-boot = &led_power;
15 led-failsafe = &led_power;
16 led-running = &led_power;
17 led-upgrade = &led_power;
18 };
19
20 keys {
21 compatible = "gpio-keys";
22
23 reset_wps {
24 label = "reset_wps";
25 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
26 linux,code = <KEY_RESTART>;
27 };
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 led_power: power {
34 label = "white:power";
35 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
36 };
37
38 internet {
39 label = "blue:internet";
40 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
41 };
42
43 wlan {
44 label = "blue:wlan";
45 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
46 };
47
48 usb {
49 label = "blue:usb";
50 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
51 trigger-sources = <&ohci_port1>, <&ehci_port1>;
52 linux,default-trigger = "usbport";
53 };
54 };
55 };
56
57 &gpio2 {
58 status = "okay";
59
60 enable_usb_power {
61 gpio-hog;
62 line-name = "enable USB power";
63 gpios = <5 GPIO_ACTIVE_HIGH>;
64 output-high;
65 };
66 };
67
68 &spi0 {
69 status = "okay";
70
71 flash@0 {
72 compatible = "jedec,spi-nor";
73 reg = <0>;
74 spi-max-frequency = <10000000>;
75
76 partitions {
77 compatible = "fixed-partitions";
78 #address-cells = <1>;
79 #size-cells = <1>;
80
81 partition@0 {
82 label = "u-boot";
83 reg = <0x0 0x30000>;
84 read-only;
85 };
86
87 partition@30000 {
88 label = "u-boot-env";
89 reg = <0x30000 0x10000>;
90 read-only;
91 };
92
93 factory: partition@40000 {
94 compatible = "nvmem-cells";
95 label = "factory";
96 reg = <0x40000 0x10000>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 read-only;
100
101 eeprom_factory_0: eeprom@0 {
102 reg = <0x0 0x200>;
103 };
104
105 macaddr_factory_4: macaddr@4 {
106 reg = <0x4 0x6>;
107 };
108 };
109
110 partition@50000 {
111 label = "cimage";
112 reg = <0x50000 0x20000>;
113 read-only;
114 };
115
116 partition@70000 {
117 compatible = "openwrt,uimage", "denx,uimage";
118 openwrt,offset = <FW_EDIMAX_OFFSET>;
119 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
120 label = "firmware";
121 reg = <0x00070000 0x00790000>;
122 };
123 };
124 };
125 };
126
127 &state_default {
128 gpio {
129 groups = "i2c", "uartf", "nd_sd";
130 function = "gpio";
131 };
132 };
133
134 &ethernet {
135 pinctrl-names = "default";
136 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
137
138 nvmem-cells = <&macaddr_factory_4>;
139 nvmem-cell-names = "mac-address";
140
141 mediatek,portmap = "wllll";
142
143 port@5 {
144 status = "okay";
145 mediatek,fixed-link = <1000 1 1 1>;
146 phy-mode = "rgmii";
147 };
148
149 mdio-bus {
150 status = "okay";
151
152 phy0: ethernet-phy@0 {
153 reg = <0>;
154 phy-mode = "rgmii";
155 };
156
157 phy1: ethernet-phy@1 {
158 reg = <1>;
159 phy-mode = "rgmii";
160 };
161
162 phy2: ethernet-phy@2 {
163 reg = <2>;
164 phy-mode = "rgmii";
165 };
166
167 phy3: ethernet-phy@3 {
168 reg = <3>;
169 phy-mode = "rgmii";
170 };
171
172 phy4: ethernet-phy@4 {
173 reg = <4>;
174 phy-mode = "rgmii";
175 };
176
177 phy1f: ethernet-phy@1f {
178 reg = <0x1f>;
179 phy-mode = "rgmii";
180 };
181 };
182 };
183
184 &gsw {
185 mediatek,ephy-base = /bits/ 8 <12>;
186 };
187
188 &wmac {
189 nvmem-cells = <&eeprom_factory_0>;
190 nvmem-cell-names = "eeprom";
191 };
192
193 &pcie {
194 status = "okay";
195 };
196
197 &pcie0 {
198 wifi@0,0 {
199 reg = <0x0000 0 0 0 0>;
200 mediatek,mtd-eeprom = <&factory 0x8000>;
201 mediatek,2ghz = <0>;
202 };
203 };
204
205 &ehci {
206 status = "okay";
207 };
208
209 &ohci {
210 status = "okay";
211 };