target/linux/ramips/dts/mt7620a_dlink_dwr-96x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * D-Link DWR-96x Common Board Description
   4  * Copyright 2022 Pawel Dembicki <paweldembicki@gmail.com>
   5  */
   6 #include "mt7620a.dtsi"
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/mtd/partitions/uimage.h>
  12
  13 / {
  14         aliases {
  15                 led-boot = &led_status;
  16                 led-failsafe = &led_status;
  17                 led-running = &led_status;
  18                 led-upgrade = &led_status;
  19         };
  20
  21         keys {
  22                 compatible = "gpio-keys";
  23
  24                 reset {
  25                         label = "reset";
  26                         gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  27                         linux,code = <KEY_RESTART>;
  28                 };
  29
  30                 wps {
  31                         label = "wps";
  32                         gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  33                         linux,code = <KEY_WPS_BUTTON>;
  34                 };
  35
  36         };
  37
  38         leds {
  39                 compatible = "gpio-leds";
  40
  41                 led_status: status {
  42                         function = LED_FUNCTION_STATUS;
  43                         color = <LED_COLOR_ID_GREEN>;
  44                         gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  45                 };
  46
  47                 wan {
  48                         function = LED_FUNCTION_WAN;
  49                         color = <LED_COLOR_ID_GREEN>;
  50                         gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  51                 };
  52
  53                 lan {
  54                         function = LED_FUNCTION_LAN;
  55                         color = <LED_COLOR_ID_GREEN>;
  56                         gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  57                 };
  58
  59                 sms {
  60                         label = "green:sms";
  61                         gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  62                 };
  63
  64                 signal_green {
  65                         label = "green:signal";
  66                         gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
  67                 };
  68
  69                 signal_red {
  70                         label = "red:signal";
  71                         gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  72                 };
  73
  74                 4g {
  75                         label = "green:4g";
  76                         gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  77                 };
  78
  79                 3g {
  80                         label = "green:3g";
  81                         gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  82                 };
  83
  84                 wlan5g {
  85                         label = "green:wlan5g";
  86                         gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  87                         linux,default-trigger = "phy0tpt";
  88                 };
  89
  90                 wlan2g {
  91                         label = "green:wlan2g";
  92                         gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  93                         linux,default-trigger = "phy1tpt";
  94                 };
  95         };
  96 };
  97
  98 &ehci {
  99         status = "okay";
 100 };
 101
 102 &gpio1 {
 103         status = "okay";
 104 };
 105
 106 &gpio2 {
 107         status = "okay";
 108 };
 109
 110 &gpio3 {
 111         status = "okay";
 112 };
 113
 114 &ohci {
 115         status = "okay";
 116 };
 117
 118 &pcie {
 119         status = "okay";
 120 };
 121
 122 &pcie0 {
 123         wifi: wifi@0,0 {
 124                 compatible = "mediatek,mt76";
 125                 reg = <0x0000 0 0 0 0>;
 126                 ieee80211-freq-limit = <5000000 6000000>;
 127         };
 128 };
 129
 130 &spi0 {
 131         status = "okay";
 132
 133         flash@0 {
 134                 compatible = "jedec,spi-nor";
 135                 reg = <0>;
 136                 spi-max-frequency = <50000000>;
 137
 138                 partitions {
 139                         compatible = "fixed-partitions";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142
 143                         partition@0 {
 144                                 label = "jboot";
 145                                 reg = <0x0 0x10000>;
 146                                 read-only;
 147                         };
 148
 149                         partition@10000 {
 150                                 compatible = "openwrt,uimage", "denx,uimage";
 151                                 openwrt,ih-magic = <IH_MAGIC_OKLI>;
 152                                 openwrt,offset = <0x10000>;
 153                                 label = "firmware";
 154                                 reg = <0x10000 0xfe0000>;
 155                         };
 156
 157                         partition@ff0000 {
 158                                 label = "config";
 159                                 reg = <0xff0000 0x10000>;
 160                                 read-only;
 161
 162                                 nvmem-layout {
 163                                         compatible = "fixed-layout";
 164                                         #address-cells = <1>;
 165                                         #size-cells = <1>;
 166
 167                                         eeprom_config_e08e: eeprom@e08e {
 168                                                 reg = <0xe08e 0x200>;
 169                                         };
 170
 171                                         eeprom_config_e29e: eeprom@e29e {
 172                                                 reg = <0xe29e 0x200>;
 173                                         };
 174
 175                                         macaddr_config_e50e: macaddr@e50e {
 176                                                 compatible = "mac-base";
 177                                                 reg = <0xe50e 0x6>;
 178                                                 #nvmem-cell-cells = <1>;
 179                                         };
 180                                 };
 181                         };
 182                 };
 183         };
 184 };
 185
 186 &state_default {
 187         default {
 188                 groups = "i2c", "wled", "spi refclk", "uartf", "ephy";
 189                 function = "gpio";
 190         };
 191 };