target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
   4  * Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "ipq8074.dtsi"
  10 #include "ipq8074-hk-cpu.dtsi"
  11 #include "ipq8074-ess.dtsi"
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/leds/common.h>
  14 #include <dt-bindings/input/input.h>
  15
  16
  17 / {
  18         model = "Zyxel NBG7815";
  19         compatible = "zyxel,nbg7815", "qcom,ipq8074";
  20
  21         aliases {
  22                 serial0 = &blsp1_uart5;
  23                 serial1 = &blsp1_uart3;
  24                 /* Alias as required by u-boot to patch MAC addresses */
  25                 ethernet0 = &dp1;
  26                 label-mac-device = &dp1;
  27         };
  28
  29         chosen {
  30                 stdout-path = "serial0:115200n8";
  31         };
  32
  33         keys {
  34                 compatible = "gpio-keys";
  35
  36                 reset {
  37                         label = "reset";
  38                         linux,code = <KEY_RESTART>;
  39                         gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
  40                 };
  41         };
  42 };
  43
  44 &tlmm {
  45         mdio_pins: mdio-pins {
  46                 mdc {
  47                         pins = "gpio68";
  48                         function = "mdc";
  49                         drive-strength = <8>;
  50                         bias-pull-up;
  51                 };
  52
  53                 mdio {
  54                         pins = "gpio69";
  55                         function = "mdio";
  56                         drive-strength = <8>;
  57                         bias-pull-up;
  58                 };
  59         };
  60 };
  61
  62
  63 &blsp1_uart3 {
  64         status = "okay";
  65 };
  66
  67 &blsp1_uart5 {
  68         status = "okay";
  69 };
  70
  71 &prng {
  72         status = "okay";
  73 };
  74
  75 &cryptobam {
  76         status = "okay";
  77 };
  78
  79 &crypto {
  80         status = "okay";
  81 };
  82
  83 &qpic_bam {
  84         status = "okay";
  85 };
  86
  87
  88 &blsp1_spi1 {
  89         pinctrl-0 = <&spi_0_pins>;
  90         pinctrl-names = "default";
  91         cs-gpios = <0>;
  92         status = "okay";
  93
  94         /*
  95          * Bootloader will find the NAND DT node by the compatible and
  96          * then "fixup" it by adding the partitions from the SMEM table
  97          * using the legacy bindings thus making it impossible for us
  98          * to change the partition table or utilize NVMEM for calibration.
  99          * So add a dummy partitions node that bootloader will populate
 100          * and set it as disabled so the kernel ignores it instead of
 101          * printing warnings due to the broken way bootloader adds the
 102          * partitions.
 103          */
 104         partitions {
 105                 status = "disabled";
 106         };
 107
 108
 109         flash@0 {
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 reg = <0>;
 113                 compatible = "jedec,spi-nor";
 114                 spi-max-frequency = <50000000>;
 115
 116                 partitions {
 117                         compatible = "fixed-partitions";
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120
 121                         partition@0 {
 122                                 label = "0:sbl1";
 123                                 reg = <0x0 0x50000>;
 124                                 read-only;
 125                         };
 126
 127                         partition@50000 {
 128                                 label = "0:mibib";
 129                                 reg = <0x50000 0x10000>;
 130                                 read-only;
 131                         };
 132
 133                         partition@60000 {
 134                                 label = "0:bootconfig";
 135                                 reg = <0x60000 0x20000>;
 136                                 read-only;
 137                         };
 138
 139                         partition@80000 {
 140                                 label = "0:bootconfig1";
 141                                 reg = <0x80000 0x20000>;
 142                                 read-only;
 143                         };
 144
 145                         partition@a0000 {
 146                                 label = "0:qsee";
 147                                 reg = <0xa0000 0x180000>;
 148                                 read-only;
 149                         };
 150
 151                         partition@220000 {
 152                                 label = "0:qsee_1";
 153                                 reg = <0x220000 0x180000>;
 154                                 read-only;
 155                         };
 156
 157                         partition@3a0000 {
 158                                 label = "0:devcfg";
 159                                 reg = <0x3a0000 0x10000>;
 160                                 read-only;
 161                         };
 162
 163                         partition@3b0000 {
 164                                 label = "0:devcfg_1";
 165                                 reg = <0x3b0000 0x10000>;
 166                                 read-only;
 167                         };
 168
 169                         partition@3c0000 {
 170                                 label = "0:apdp";
 171                                 reg = <0x3c0000 0x10000>;
 172                                 read-only;
 173                         };
 174
 175                         partition@3d0000 {
 176                                 label = "0:apdp_1";
 177                                 reg = <0x3d0000 0x10000>;
 178                                 read-only;
 179                         };
 180
 181                         partition@3e0000 {
 182                                 label = "0:rpm";
 183                                 reg = <0x3e0000 0x40000>;
 184                                 read-only;
 185                         };
 186
 187                         partition@420000 {
 188                                 label = "0:rpm_1";
 189                                 reg = <0x420000 0x40000>;
 190                                 read-only;
 191                         };
 192
 193                         partition@460000 {
 194                                 label = "0:cdt";
 195                                 reg = <0x460000 0x10000>;
 196                                 read-only;
 197                         };
 198
 199                         partition@470000 {
 200                                 label = "0:cdt_1";
 201                                 reg = <0x470000 0x10000>;
 202                                 read-only;
 203                         };
 204
 205                         partition@480000 {
 206                                 label = "0:appsbl";
 207                                 reg = <0x480000 0xc0000>;
 208                                 read-only;
 209                         };
 210
 211                         partition@540000 {
 212                                 label = "0:appsbl_1";
 213                                 reg = <0x540000 0xc0000>;
 214                                 read-only;
 215                         };
 216
 217                         partition@600000 {
 218                                 compatible = "u-boot,env";
 219                                 label = "0:appsblenv";
 220                                 reg = <0x600000 0x10000>;
 221
 222                                 macaddr_lan: ethaddr {
 223                                         #nvmem-cell-cells = <1>;
 224                                 };
 225                         };
 226
 227                         partition@610000 {
 228                                 label = "0:art";
 229                                 reg = <0x610000 0x40000>;
 230                                 read-only;
 231                         };
 232
 233                         partition@650000 {
 234                                 label = "0:ethphyfw";
 235                                 reg = <0x650000 0x80000>;
 236                                 read-only;
 237
 238                                 nvmem-layout {
 239                                         compatible = "fixed-layout";
 240
 241                                         aqr_fw: aqr-fw@0 {
 242                                                 /* Skip the QCOM MBN Header of 40 bytes */
 243                                                 reg = <0x28 0x5f402>;
 244                                         };
 245                                 };
 246                         };
 247
 248                         partition@6d0000 {
 249                                 label = "0:crt";
 250                                 reg = <0x6d0000 0x10000>;
 251                                 read-only;
 252                         };
 253
 254                         partition@6e0000 {
 255                                 label = "dual_flag";
 256                                 reg = <0x6e0000 0x10000>;
 257                         };
 258
 259                         partition@6f0000 {
 260                                 label = "reserved";
 261                                 reg = <0x6f0000 0x110000>;
 262                                 read-only;
 263                         };
 264                 };
 265         };
 266 };
 267
 268 &mdio {
 269         status = "okay";
 270         pinctrl-0 = <&mdio_pins>;
 271         pinctrl-names = "default";
 272         reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 273
 274         ethernet-phy-package@0 {
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 compatible = "qcom,qca8075-package";
 278                 reg = <0>;
 279
 280                 qca8075_0: ethernet-phy@0 {
 281                         compatible = "ethernet-phy-ieee802.3-c22";
 282                         reg = <0>;
 283                 };
 284
 285                 qca8075_1: ethernet-phy@1 {
 286                         compatible = "ethernet-phy-ieee802.3-c22";
 287                         reg = <1>;
 288                 };
 289
 290                 qca8075_2: ethernet-phy@2 {
 291                         compatible = "ethernet-phy-ieee802.3-c22";
 292                         reg = <2>;
 293                 };
 294
 295                 qca8075_3: ethernet-phy@3 {
 296                         compatible = "ethernet-phy-ieee802.3-c22";
 297                         reg = <3>;
 298                 };
 299         };
 300
 301         qca8081: ethernet-phy@28 {
 302                 compatible = "ethernet-phy-id004d.d101";
 303                 reg = <28>;
 304                 reset-deassert-us = <10000>;
 305                 reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
 306         };
 307
 308         aqr113c: ethernet-phy@5 {
 309                 compatible = "ethernet-phy-ieee802.3-c45";
 310                 reg = <8>;
 311                 reset-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
 312
 313                 nvmem-cells = <&aqr_fw>;
 314                 nvmem-cell-names = "firmware";
 315         };
 316 };
 317
 318 &switch {
 319         status = "okay";
 320
 321         switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>;
 322         switch_wan_bmp = <ESS_PORT5>;
 323         switch_mac_mode = <MAC_MODE_PSGMII>;
 324         switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>;
 325         switch_mac_mode2 = <MAC_MODE_USXGMII>;
 326
 327         qcom,port_phyinfo {
 328                 port@1 {
 329                         port_id = <1>;
 330                         phy_address = <0>;
 331                 };
 332
 333                 port@2 {
 334                         port_id = <2>;
 335                         phy_address = <1>;
 336                 };
 337
 338                 port@3 {
 339                         port_id = <3>;
 340                         phy_address = <2>;
 341                 };
 342
 343                 port@4 {
 344                         port_id = <4>;
 345                         phy_address = <3>;
 346                 };
 347
 348                 port@5 {
 349                         port_id = <5>;
 350                         phy_address = <28>;
 351                         port_mac_sel = "QGMAC_PORT";
 352                 };
 353
 354                 port@6 {
 355                         port_id = <6>;
 356                         ethernet-phy-ieee802.3-c45;
 357                         phy_address = <8>;
 358                 };
 359         };
 360 };
 361
 362 &edma {
 363         status = "okay";
 364 };
 365
 366 &dp1 {
 367         status = "okay";
 368         phy-handle = <&qca8075_0>;
 369         label = "lan1";
 370         nvmem-cells = <&macaddr_lan 0>;
 371         nvmem-cell-names = "mac-address";
 372 };
 373
 374 &dp2 {
 375         status = "okay";
 376         phy-handle = <&qca8075_1>;
 377         label = "lan2";
 378         nvmem-cells = <&macaddr_lan 0>;
 379         nvmem-cell-names = "mac-address";
 380 };
 381
 382 &dp3 {
 383         status = "okay";
 384         phy-handle = <&qca8075_2>;
 385         label = "lan3";
 386         nvmem-cells = <&macaddr_lan 0>;
 387         nvmem-cell-names = "mac-address";
 388 };
 389
 390 &dp4 {
 391         status = "okay";
 392         phy-handle = <&qca8075_3>;
 393         label = "lan4";
 394         nvmem-cells = <&macaddr_lan 0>;
 395         nvmem-cell-names = "mac-address";
 396 };
 397
 398 &dp5 {
 399         status = "okay";
 400         phy-handle = <&qca8081>;
 401         label = "wan";
 402         nvmem-cells = <&macaddr_lan 1>;
 403         nvmem-cell-names = "mac-address";
 404 };
 405
 406 &dp6_syn {
 407         status = "okay";
 408         phy-mode = "usxgmii";
 409         phy-handle = <&aqr113c>;
 410         label = "10g";
 411         nvmem-cells = <&macaddr_lan 0>;
 412         nvmem-cell-names = "mac-address";
 413 };
 414
 415 &blsp1_i2c2 {
 416         pinctrl-0 = <&i2c_0_pins>;
 417         pinctrl-names = "default";
 418         status = "okay";
 419
 420         tmp103@70 {
 421                 compatible = "ti,tmp103";
 422                 reg = <0x70>;
 423         };
 424 };
 425
 426 &sdhc_1 {
 427         status = "okay";
 428         /* unstable, problem with the hs400 > h200 speed switch */
 429         /delete-property/ mmc-hs400-1_8v;
 430         mmc-hs200-1_8v;
 431         mmc-ddr-1_8v;
 432         vqmmc-supply = <&l11>;
 433 };
 434
 435 &ssphy_0 {
 436         status = "okay";
 437 };
 438
 439 &qusb_phy_0 {
 440         status = "okay";
 441 };
 442
 443 &ssphy_1 {
 444         status = "okay";
 445 };
 446
 447 &qusb_phy_1 {
 448         status = "okay";
 449 };
 450
 451 &usb_0 {
 452         status = "okay";
 453 };
 454
 455 &usb_1 {
 456         status = "okay";
 457 };
 458
 459 &wifi {
 460         status = "okay";
 461
 462         qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
 463 };