target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /* Copyright 2023 Nokia */
   3
   4 /dts-v1/;
   5
   6 #include "ipq8074.dtsi"
   7 #include "ipq8074-hk-cpu.dtsi"
   8 #include "ipq8074-ess.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/leds/common.h>
  12
  13 / {
  14         model = "Compex WPQ873";
  15         compatible = "compex,wpq873", "qcom,ipq8074";
  16
  17         aliases {
  18                 serial0 = &blsp1_uart5;
  19                 led-boot = &led_power_blue;
  20                 led-failsafe = &led_power_red;
  21                 led-running = &led_system_green;
  22                 led-upgrade = &led_system_blue;
  23                 /* Aliases as required by u-boot to patch MAC addresses */
  24                 ethernet0 = &dp6;
  25                 ethernet1 = &dp2;
  26                 ethernet2 = &dp3;
  27                 ethernet3 = &dp4;
  28                 label-mac-device = &dp6;
  29         };
  30
  31         chosen {
  32                 stdout-path = "serial0:115200n8";
  33                 bootargs-append = " root=/dev/ubiblock0_1";
  34         };
  35
  36         keys {
  37                 compatible = "gpio-keys";
  38
  39                 reset {
  40                         label = "reset";
  41                         gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_RESTART>;
  43                 };
  44         };
  45
  46         leds {
  47                 compatible = "gpio-leds";
  48
  49                 led_power_red: power-red {
  50                         gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
  51                         color = <LED_COLOR_ID_RED>;
  52                 };
  53
  54                 led_power_blue: power-blue {
  55                         gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
  56                         color = <LED_COLOR_ID_BLUE>;
  57                 };
  58
  59                 led_system_red: system-red {
  60                         gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
  61                         color = <LED_COLOR_ID_RED>;
  62                 };
  63
  64                 led_system_green: system-green {
  65                         gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
  66                         color = <LED_COLOR_ID_GREEN>;
  67                 };
  68
  69                 led_system_blue: system-blue {
  70                         gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
  71                         color = <LED_COLOR_ID_BLUE>;
  72                 };
  73         };
  74 };
  75
  76 &tlmm {
  77         mdio_pins: mdio-pins {
  78                 mdc {
  79                         pins = "gpio68";
  80                         function = "mdc";
  81                         drive-strength = <8>;
  82                         bias-pull-up;
  83                 };
  84
  85                 mdio {
  86                         pins = "gpio69";
  87                         function = "mdio";
  88                         drive-strength = <8>;
  89                         bias-pull-up;
  90                 };
  91         };
  92
  93         i2c_pins: i2c-pins {
  94                 pins = "gpio0", "gpio2";
  95                 function = "blsp5_i2c";
  96                 drive-strength = <8>;
  97                 bias-disable;
  98         };
  99 };
 100
 101 &blsp1_uart5 {
 102         status = "okay";
 103 };
 104
 105 &blsp1_i2c6 {
 106         status = "okay";
 107
 108         pinctrl-0 = <&i2c_pins>;
 109         pinctrl-names = "default";
 110 };
 111
 112 &prng {
 113         status = "okay";
 114 };
 115
 116 &cryptobam {
 117         status = "okay";
 118 };
 119
 120 &crypto {
 121         status = "okay";
 122 };
 123
 124 &qpic_bam {
 125         status = "okay";
 126 };
 127
 128 &blsp1_spi1 {
 129         status = "okay";
 130 };
 131
 132 &tlmm {
 133         mdio_pins: mdio-pins {
 134                 mdc {
 135                         pins = "gpio68";
 136                         function = "mdc";
 137                         drive-strength = <8>;
 138                         bias-pull-up;
 139                 };
 140
 141                 mdio {
 142                         pins = "gpio69";
 143                         function = "mdio";
 144                         drive-strength = <8>;
 145                         bias-pull-up;
 146                 };
 147         };
 148
 149         button_pins: button_pins {
 150                 reset_button {
 151                         pins = "gpio66";
 152                         function = "gpio";
 153                         drive-strength = <8>;
 154                         bias-pull-up;
 155                 };
 156         };
 157 };
 158
 159 &blsp1_spi1 {
 160         status = "okay";
 161
 162         flash@0 {
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 reg = <0>;
 166                 compatible = "jedec,spi-nor";
 167                 spi-max-frequency = <50000000>;
 168
 169                 partitions {
 170                         compatible = "fixed-partitions";
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173
 174                         partition@0 {
 175                                 label = "0:sbl1";
 176                                 reg = <0x0 0x50000>;
 177                                 read-only;
 178                         };
 179
 180                         partition@50000 {
 181                                 label = "0:mibib";
 182                                 reg = <0x50000 0x10000>;
 183                                 read-only;
 184                         };
 185
 186                         partition@60000 {
 187                                 label = "0:bootconfig";
 188                                 reg = <0x60000 0x20000>;
 189                                 read-only;
 190                         };
 191
 192                         partition@80000 {
 193                                 label = "0:bootconfig1";
 194                                 reg = <0x80000 0x20000>;
 195                                 read-only;
 196                         };
 197
 198                         partition@a0000 {
 199                                 label = "0:qsee";
 200                                 reg = <0xa0000 0x180000>;
 201                                 read-only;
 202                         };
 203
 204                         partition@220000 {
 205                                 label = "0:qsee_1";
 206                                 reg = <0x220000 0x180000>;
 207                                 read-only;
 208                         };
 209
 210                         partition@3a0000 {
 211                                 label = "0:devcfg";
 212                                 reg = <0x3a0000 0x10000>;
 213                                 read-only;
 214                         };
 215
 216                         partition@3b0000 {
 217                                 label = "0:devcfg_1";
 218                                 reg = <0x3b0000 0x10000>;
 219                                 read-only;
 220                         };
 221
 222                         partition@3c0000 {
 223                                 label = "0:apdp";
 224                                 reg = <0x3c0000 0x10000>;
 225                                 read-only;
 226                         };
 227
 228                         partition@3d0000 {
 229                                 label = "0:apdp_1";
 230                                 reg = <0x3d0000 0x10000>;
 231                                 read-only;
 232                         };
 233
 234                         partition@3e0000 {
 235                                 label = "0:rpm";
 236                                 reg = <0x3e0000 0x40000>;
 237                                 read-only;
 238                         };
 239
 240                         partition@420000 {
 241                                 label = "0:rpm_1";
 242                                 reg = <0x420000 0x40000>;
 243                                 read-only;
 244                         };
 245
 246                         partition@460000 {
 247                                 label = "0:cdt";
 248                                 reg = <0x460000 0x10000>;
 249                                 read-only;
 250                         };
 251
 252                         partition@470000 {
 253                                 label = "0:cdt_1";
 254                                 reg = <0x470000 0x10000>;
 255                                 read-only;
 256                         };
 257
 258                         partition@480000 {
 259                                 label = "0:appsblenv";
 260                                 reg = <0x480000 0x10000>;
 261                         };
 262
 263                         partition@490000 {
 264                                 label = "0:appsbl";
 265                                 reg = <0x490000 0xa0000>;
 266                                 read-only;
 267                         };
 268
 269                         partition@550000 {
 270                                 label = "0:appsbl_1";
 271                                 reg = <0x530000 0xa0000>;
 272                                 read-only;
 273                         };
 274
 275                         partition@610000 {
 276                                 label = "0:art";
 277                                 reg = <0x5d0000 0x40000>;
 278                                 read-only;
 279                         };
 280
 281                         partition@650000 {
 282                                 label = "0:ethphyfw";
 283                                 reg = <0x610000 0x80000>;
 284                                 read-only;
 285                         };
 286                 };
 287         };
 288 };
 289
 290 &qpic_nand {
 291         status = "okay";
 292
 293         nand@0 {
 294                 reg = <0>;
 295                 nand-ecc-strength = <8>;
 296                 nand-ecc-step-size = <512>;
 297                 nand-bus-width = <8>;
 298
 299                 partitions {
 300                         compatible = "fixed-partitions";
 301                         #address-cells = <1>;
 302                         #size-cells = <1>;
 303
 304                         partition@0 {
 305                                 label = "rootfs";
 306                                 reg = <0x0000000 0x3400000>;
 307                         };
 308
 309                         partition@3400000 {
 310                                 label = "0:wififw";
 311                                 reg = <0x3400000 0x800000>;
 312                                 read-only;
 313                         };
 314
 315                         partition@3c00000 {
 316                                 label = "rootfs_1";
 317                                 reg = <0x3c00000 0x3400000>;
 318                         };
 319
 320                         partition@7000000 {
 321                                 label = "0:wififw_1";
 322                                 reg = <0x7000000 0x800000>;
 323                                 read-only;
 324                         };
 325                 };
 326         };
 327 };
 328
 329 &qusb_phy_0 {
 330         status = "okay";
 331 };
 332
 333 &qusb_phy_1 {
 334         status = "okay";
 335 };
 336
 337 &ssphy_0 {
 338         status = "okay";
 339 };
 340
 341 &ssphy_1 {
 342         status = "okay";
 343 };
 344
 345 &usb_0 {
 346         status = "okay";
 347 };
 348
 349 &usb_1 {
 350         status = "okay";
 351 };
 352
 353
 354 &mdio {
 355         status = "okay";
 356         pinctrl-0 = <&mdio_pins>;
 357         pinctrl-names = "default";
 358         reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 359
 360         ethernet-phy-package@0 {
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 compatible = "qcom,qca8075-package";
 364                 reg = <0>;
 365
 366                 qca8075_1: ethernet-phy@1 {
 367                         compatible = "ethernet-phy-ieee802.3-c22";
 368                         reg = <1>;
 369                 };
 370
 371                 qca8075_2: ethernet-phy@2 {
 372                         compatible = "ethernet-phy-ieee802.3-c22";
 373                         reg = <2>;
 374                 };
 375
 376                 qca8075_3: ethernet-phy@3 {
 377                         compatible = "ethernet-phy-ieee802.3-c22";
 378                         reg = <3>;
 379                 };
 380         };
 381
 382         qca8081: ethernet-phy@28 {
 383                 compatible = "ethernet-phy-ieee802.3-c22";
 384                 reg = <28>;
 385                 reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
 386         };
 387
 388 };
 389
 390 &switch {
 391         status = "okay";
 392
 393         switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
 394         switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
 395         switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
 396         switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance1*/
 397         switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
 398
 399         qcom,port_phyinfo {
 400                 port@2 {
 401                         port_id = <2>;
 402                         phy_address = <1>;
 403                 };
 404                 port@3 {
 405                         port_id = <3>;
 406                         phy_address = <2>;
 407                 };
 408                 port@4 {
 409                         port_id = <4>;
 410                         phy_address = <3>;
 411                 };
 412                 port@6 {
 413                         port_id = <6>;
 414                         phy_address = <28>;
 415                         port_mac_sel = "QGMAC_PORT";
 416                 };
 417         };
 418 };
 419
 420 &edma {
 421         status = "okay";
 422 };
 423
 424 &dp2 {
 425         status = "okay";
 426         phy-handle = <&qca8075_1>;
 427         label = "lan1";
 428 };
 429
 430 &dp3 {
 431         status = "okay";
 432         phy-handle = <&qca8075_2>;
 433         label = "lan2";
 434 };
 435
 436 &dp4 {
 437         status = "okay";
 438         phy-handle = <&qca8075_3>;
 439         label = "lan3";
 440 };
 441
 442 &dp6 {
 443         status = "okay";
 444         phy-handle = <&qca8081>;
 445         label = "wan";
 446 };
 447
 448 &pcie_qmp0 {
 449         status = "okay";
 450 };
 451
 452 &pcie0 {
 453         status = "okay";
 454
 455         perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
 456
 457         bridge@0,0 {
 458                 reg = <0x00020000 0 0 0 0>;
 459                 #address-cells = <3>;
 460                 #size-cells = <2>;
 461                 ranges;
 462         };
 463 };
 464
 465 &pcie_qmp1 {
 466         status = "okay";
 467 };
 468
 469 &pcie1 {
 470         status = "okay";
 471
 472         perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
 473
 474         bridge@1,0 {
 475                 reg = <0x00010000 0 0 0 0>;
 476                 #address-cells = <3>;
 477                 #size-cells = <2>;
 478                 ranges;
 479         };
 480 };
 481
 482 &wifi {
 483         status = "okay";
 484
 485         qcom,ath11k-calibration-variant = "Compex-WPQ873";
 486 };