target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4
   5 #include "ipq8074.dtsi"
   6 #include "ipq8074-hk-cpu.dtsi"
   7 #include "ipq8074-ess.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/leds/common.h>
  11
  12 / {
  13         model = "prpl Foundation Haze";
  14         compatible = "prpl,haze", "qcom,ipq8074";
  15
  16         aliases {
  17                 serial0 = &blsp1_uart5;
  18                 /* Aliases are required by U-Boot to patch MAC addresses */
  19                 ethernet0 = &dp6_syn;
  20                 ethernet1 = &dp4;
  21                 ethernet2 = &dp3;
  22                 ethernet3 = &dp2;
  23                 label-mac-device = &dp6_syn;
  24                 led-boot = &led_system_blue;
  25                 led-failsafe = &led_system_red;
  26                 led-running = &led_system_green;
  27                 led-upgrade = &led_system_blue;
  28         };
  29
  30         chosen {
  31                 stdout-path = "serial0:115200n8";
  32         };
  33
  34         keys {
  35                 compatible = "gpio-keys";
  36                 pinctrl-0 = <&button_pins>;
  37                 pinctrl-names = "default";
  38
  39                 wps-button {
  40                         label = "wps";
  41                         gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_WPS_BUTTON>;
  43                 };
  44
  45                 reset-button {
  46                         label = "reset";
  47                         gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  48                         linux,code = <KEY_RESTART>;
  49                 };
  50         };
  51 };
  52
  53 &tlmm {
  54         mdio_pins: mdio-state {
  55                 mdc-pins {
  56                         pins = "gpio68";
  57                         function = "mdc";
  58                         drive-strength = <8>;
  59                         bias-pull-up;
  60                 };
  61
  62                 mdio-pins {
  63                         pins = "gpio69";
  64                         function = "mdio";
  65                         drive-strength = <8>;
  66                         bias-pull-up;
  67                 };
  68         };
  69
  70         button_pins: button-state {
  71                 wps-pins {
  72                         pins = "gpio42";
  73                         function = "gpio";
  74                         drive-strength = <8>;
  75                         bias-pull-up;
  76                 };
  77
  78                 rst-pins {
  79                         pins = "gpio44";
  80                         function = "gpio";
  81                         drive-strength = <8>;
  82                         bias-pull-up;
  83                 };
  84         };
  85
  86         i2c_3_pins: i2c-3-state {
  87                 pins = "gpio46", "gpio47";
  88                 function = "blsp2_i2c";
  89                 drive-strength = <8>;
  90                 bias-disable;
  91         };
  92 };
  93
  94 &blsp1_uart5 {
  95         status = "okay";
  96 };
  97
  98 &prng {
  99         status = "okay";
 100 };
 101
 102 &ssphy_0 {
 103         status = "okay";
 104 };
 105
 106 &qusb_phy_0 {
 107         status = "okay";
 108 };
 109
 110 &ssphy_1 {
 111         status = "okay";
 112 };
 113
 114 &qusb_phy_1 {
 115         status = "okay";
 116 };
 117
 118 &usb_0 {
 119         status = "okay";
 120 };
 121
 122 &usb_1 {
 123         status = "okay";
 124 };
 125
 126 &cryptobam {
 127         status = "okay";
 128 };
 129
 130 &crypto {
 131         status = "okay";
 132 };
 133
 134 &qpic_bam {
 135         status = "okay";
 136 };
 137
 138 &blsp1_spi1 { /* BLSP1 QUP1 */
 139         pinctrl-0 = <&spi_0_pins>;
 140         pinctrl-names = "default";
 141         cs-gpios = <0>;
 142         status = "okay";
 143
 144         flash@0 {
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 reg = <0>;
 148                 compatible = "jedec,spi-nor";
 149                 spi-max-frequency = <50000000>;
 150
 151                 partitions {
 152                         compatible = "qcom,smem-part";
 153                 };
 154         };
 155 };
 156
 157 &mdio {
 158         status = "okay";
 159
 160         pinctrl-0 = <&mdio_pins>;
 161         pinctrl-names = "default";
 162         reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
 163
 164         ethernet-phy-package@0 {
 165                 #address-cells = <1>;
 166                 #size-cells = <0>;
 167                 compatible = "qcom,qca8075-package";
 168                 reg = <0>;
 169
 170                 qca8075_0: ethernet-phy@0 {
 171                         compatible = "ethernet-phy-ieee802.3-c22";
 172                         reg = <0>;
 173                 };
 174
 175                 qca8075_1: ethernet-phy@1 {
 176                         compatible = "ethernet-phy-ieee802.3-c22";
 177                         reg = <1>;
 178                 };
 179
 180                 qca8075_2: ethernet-phy@2 {
 181                         compatible = "ethernet-phy-ieee802.3-c22";
 182                         reg = <2>;
 183                 };
 184
 185                 qca8075_3: ethernet-phy@3 {
 186                         compatible = "ethernet-phy-ieee802.3-c22";
 187                         reg = <3>;
 188                 };
 189         };
 190
 191         aqr113c: ethernet-phy@5 {
 192                 compatible ="ethernet-phy-ieee802.3-c45";
 193                 reg = <8>;
 194                 reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
 195         };
 196 };
 197
 198 &sdhc_1 {
 199         status = "okay";
 200
 201         vqmmc-supply = <&l11>;
 202 };
 203
 204 &switch {
 205         status = "okay";
 206
 207         switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
 208         switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
 209         switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
 210         switch_mac_mode1 = <MAC_MODE_10GBASE_R>; /* mac mode for uniphy instance1*/
 211         switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
 212
 213         qcom,port_phyinfo {
 214                 port@1 {
 215                         port_id = <1>;
 216                         phy_address = <0>;
 217                 };
 218                 port@2 {
 219                         port_id = <2>;
 220                         phy_address = <1>;
 221                 };
 222                 port@3 {
 223                         port_id = <3>;
 224                         phy_address = <2>;
 225                 };
 226                 port@4 {
 227                         port_id = <4>;
 228                         phy_address = <3>;
 229                 };
 230                 port@6 {
 231                         port_id = <6>;
 232                         phy_address = <8>;
 233                         compatible = "ethernet-phy-ieee802.3-c45";
 234                         ethernet-phy-ieee802.3-c45;
 235                 };
 236         };
 237 };
 238
 239 &edma {
 240         status = "okay";
 241 };
 242
 243 /* Dummy LAN port */
 244 &dp1 {
 245         status = "disabled";
 246         phy-handle = <&qca8075_0>;
 247         label = "lan4";
 248 };
 249
 250 &dp2 {
 251         status = "okay";
 252         phy-handle = <&qca8075_1>;
 253         label = "lan3";
 254 };
 255
 256 &dp3 {
 257         status = "okay";
 258         phy-handle = <&qca8075_2>;
 259         label = "lan2";
 260 };
 261
 262 &dp4 {
 263         status = "okay";
 264         phy-handle = <&qca8075_3>;
 265         label = "lan1";
 266 };
 267
 268 &dp6_syn {
 269         status = "okay";
 270         qcom,mactype = <1>;
 271         phy-mode = "usxgmii";
 272         phy-handle = <&aqr113c>;
 273         label = "wan";
 274 };
 275
 276 &pcie_qmp0 {
 277         status = "okay";
 278 };
 279
 280 &pcie0 {
 281         status = "okay";
 282
 283         perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
 284
 285         bridge@0,0 {
 286                 reg = <0x00020000 0 0 0 0>;
 287                 #address-cells = <3>;
 288                 #size-cells = <2>;
 289                 ranges;
 290         };
 291 };
 292
 293 &pcie_qmp1 {
 294         status = "okay";
 295 };
 296
 297 &pcie1 {
 298         status = "okay";
 299
 300         perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
 301
 302         bridge@1,0 {
 303                 reg = <0x00010000 0 0 0 0>;
 304                 #address-cells = <3>;
 305                 #size-cells = <2>;
 306                 ranges;
 307
 308                 wifi@1,0 {
 309                         status = "okay";
 310
 311                         /* ath11k has no DT compatible for PCI cards */
 312                         compatible = "pci17cb,1104";
 313                         reg = <0x00010000 0 0 0 0>;
 314
 315                         qcom,ath11k-calibration-variant = "prpl-Haze";
 316                 };
 317         };
 318 };
 319
 320 &wifi {
 321         status = "okay";
 322
 323         qcom,ath11k-calibration-variant = "prpl-Haze";
 324 };
 325
 326 &blsp1_i2c3{
 327         pinctrl-0 = <&i2c_3_pins>;
 328         pinctrl-names = "default";
 329         status = "okay";
 330
 331         led-controller@30 {
 332                 compatible = "ti,lp5562";
 333                 reg = <0x30>;
 334                 clock-mode = /bits/ 8 <2>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337
 338                 led_system_red: chan@0 {
 339                         chan-name = "red";
 340                         led-cur = /bits/ 8 <0x20>;
 341                         max-cur = /bits/ 8 <0x60>;
 342                         color = <LED_COLOR_ID_RED>;
 343                         reg = <0>;
 344                 };
 345
 346                 led_system_green: chan@1 {
 347                         chan-name = "green";
 348                         led-cur = /bits/ 8 <0x20>;
 349                         max-cur = /bits/ 8 <0x60>;
 350                         color = <LED_COLOR_ID_GREEN>;
 351                         reg = <1>;
 352                 };
 353
 354                 led_system_blue: chan@2 {
 355                         chan-name = "blue";
 356                         led-cur = /bits/ 8 <0x20>;
 357                         max-cur = /bits/ 8 <0x60>;
 358                         color = <LED_COLOR_ID_BLUE>;
 359                         reg = <2>;
 360                 };
 361         };
 362 };