target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "cn71xx.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "ubnt,edgerouter-e300", "cavium,cn7130";
  11         model = "Ubiquiti EdgeRouter E300 series";
  12
  13         aliases {
  14                 /* White + Blinking Blue */
  15                 led-boot = &led_power_white;
  16                 /* Blue + Blinking White */
  17                 led-failsafe = &led_power_blue;
  18                 /* Constant Blue */
  19                 led-running = &led_power_blue;
  20                 /* Blue + Blinking White */
  21                 led-upgrade = &led_power_blue;
  22         };
  23
  24         memory@0 {
  25                 device_type = "memory";
  26                 reg = <0x0 0x00000000>,
  27                       <0x0 0x10000000>,
  28                       <0x0 0x20000000>,
  29                       <0x0 0x30000000>;
  30         };
  31
  32         leds {
  33                 compatible = "gpio-leds";
  34
  35                 led_power_blue: power_blue {
  36                         function = LED_FUNCTION_POWER;
  37                         color = <LED_COLOR_ID_BLUE>;
  38                         gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
  39                 };
  40
  41                 led_power_white: power_white {
  42                         function = LED_FUNCTION_POWER;
  43                         color = <LED_COLOR_ID_WHITE>;
  44                         gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
  45                 };
  46         };
  47
  48         keys {
  49                 compatible = "gpio-keys-polled";
  50                 poll-interval = <20>;
  51
  52                 reset {
  53                         label = "reset";
  54                         linux,code = <KEY_RESTART>;
  55                         gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  56                         debounce-interval = <60>;
  57                 };
  58         };
  59
  60         sfp: sfp {
  61                 compatible = "sff,sfp";
  62                 i2c-bus = <&twsi0>;
  63                 /* Pins 12, 13 and 14 gets pulled low when SFP is plugged in */
  64                 mod-def0-gpio = <&gpio 12 GPIO_ACTIVE_LOW>;
  65         };
  66 };
  67
  68 &uart0 {
  69         status = "okay";
  70 };
  71
  72 &usb0 {
  73         status = "okay";
  74 };
  75
  76 &xhci0 {
  77         status = "okay";
  78         dr_mode = "host";
  79 };
  80
  81 &twsi0 {
  82         status = "okay";
  83
  84         sfp_eeprom@50 {
  85                 compatible = "at,24c04";
  86                 reg = <0x50>;
  87         };
  88
  89         sfp_eeprom@51 {
  90                 compatible = "at,24c04";
  91                 reg = <0x51>;
  92         };
  93 };
  94
  95 &spi {
  96         status = "okay";
  97
  98         flash@0 {
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 compatible = "Macronix,mx25l6405d", "spi-flash";
 102                 reg = <0>;
 103                 spi-max-frequency = <25000000>;
 104
 105                 partitions {
 106                         compatible = "fixed-partitions";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109
 110                         partition@0 {
 111                                 label = "boot0";
 112                                 read-only;
 113                                 reg = <0x000000 0x300000>;
 114                         };
 115
 116                         partition@300000 {
 117                                 label = "dummy";
 118                                 read-only;
 119                                 reg = <0x300000 0x100000>;
 120                         };
 121
 122                         partition@400000 {
 123                                 label = "eeprom";
 124                                 read-only;
 125                                 reg = <0x400000 0x10000>;
 126
 127                                 nvmem-layout {
 128                                         compatible = "fixed-layout";
 129                                         #address-cells = <1>;
 130                                         #size-cells = <1>;
 131
 132                                         macaddr_eeprom_0: macaddr@0 {
 133                                                 compatible = "mac-base";
 134                                                 reg = <0x0 0x6>;
 135                                                 #nvmem-cell-cells = <1>;
 136                                         };
 137                                 };
 138                         };
 139                 };
 140         };
 141 };
 142
 143 &mmc {
 144         status = "okay";
 145
 146         mmc-slot@0 {
 147                 compatible = "mmc-slot";
 148                 reg = <0>;
 149                 non-removable;
 150                 max-frequency = <26000000>;
 151                 voltage-ranges = <3300 3300>;
 152                 bus-width = <8>;
 153         };
 154 };
 155
 156 &smi0 {
 157         status = "okay";
 158
 159         phy4: ethernet-phy@4 {
 160                 device_type = "ethernet-phy";
 161                 interrupts = <17 8>;
 162                 interrupt-parent = <&gpio>;
 163                 compatible = "vitesse,vsc8504", "ethernet-phy-ieee802.3-c22";
 164                 reg = <4>;
 165                 sfp = <&sfp>;
 166         };
 167
 168         phy5: ethernet-phy@5 {
 169                 device_type = "ethernet-phy";
 170                 interrupts = <17 8>;
 171                 interrupt-parent = <&gpio>;
 172                 compatible = "vitesse,vsc8504", "ethernet-phy-ieee802.3-c22";
 173                 reg = <5>;
 174         };
 175
 176         phy6: ethernet-phy@6 {
 177                 device_type = "ethernet-phy";
 178                 interrupts = <17 8>;
 179                 interrupt-parent = <&gpio>;
 180                 compatible = "vitesse,vsc8504", "ethernet-phy-ieee802.3-c22";
 181                 reg = <6>;
 182         };
 183
 184         phy7: ethernet-phy@7 {
 185                 device_type = "ethernet-phy";
 186                 interrupts = <17 8>;
 187                 interrupt-parent = <&gpio>;
 188                 compatible = "vitesse,vsc8504", "ethernet-phy-ieee802.3-c22";
 189                 reg = <7>;
 190         };
 191 };
 192
 193 &pip {
 194         status = "okay";
 195
 196         interface@0 {
 197                 status = "okay";
 198
 199                 ethernet@1 {
 200                         label = "lan0";
 201                         status = "okay";
 202                         phy-mode = "sgmii";
 203                         phy-handle = <&phy5>;
 204                         nvmem-cells = <&macaddr_eeprom_0 1>;
 205                         nvmem-cell-names = "mac-address";
 206                 };
 207
 208                 ethernet@2 {
 209                         label = "lan1";
 210                         status = "okay";
 211                         phy-mode = "sgmii";
 212                         phy-handle = <&phy6>;
 213                         nvmem-cells = <&macaddr_eeprom_0 2>;
 214                         nvmem-cell-names = "mac-address";
 215                 };
 216
 217                 ethernet@3 {
 218                         label = "lan2";
 219                         status = "okay";
 220                         phy-mode = "sgmii";
 221                         phy-handle = <&phy7>;
 222                         nvmem-cells = <&macaddr_eeprom_0 3>;
 223                         nvmem-cell-names = "mac-address";
 224                 };
 225         };
 226 };