mvebu: add ClearFog .tar.gz bundle
[openwrt/openwrt.git] / target / linux / mvebu / patches-4.4 / 024-mvebu-make-device-IO-strongly-ordered.patch
1 On Cortex-A9 based Marvell SoCs, when HW I/O coherency is enabled, all
2 non-RAM space needs to be mapped strongly ordered.
3 In upstream this was added for PCIe I/O only, this change expands it
4 to cover all device memory. Fixes issues with CESA.
5 Based on patch from Thomas Petazzoni.
6
7 Signed-off-by: Felix Fietkau <nbd@nbd.name>
8
9 --- a/arch/arm/mach-mvebu/coherency.c
10 +++ b/arch/arm/mach-mvebu/coherency.c
11 @@ -162,22 +162,16 @@ exit:
12 }
13
14 /*
15 - * This ioremap hook is used on Armada 375/38x to ensure that PCIe
16 + * This ioremap hook is used on Armada 375/38x to ensure that all non-RAM
17 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
18 - * is needed as a workaround for a deadlock issue between the PCIe
19 + * is needed as a workaround for a deadlock issue between the bus
20 * interface and the cache controller.
21 */
22 static void __iomem *
23 -armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
24 - unsigned int mtype, void *caller)
25 +armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
26 + unsigned int mtype, void *caller)
27 {
28 - struct resource pcie_mem;
29 -
30 - mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
31 -
32 - if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
33 - mtype = MT_UNCACHED;
34 -
35 + mtype = MT_UNCACHED;
36 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
37 }
38
39 @@ -186,7 +180,7 @@ static void __init armada_375_380_cohere
40 struct device_node *cache_dn;
41
42 coherency_cpu_base = of_iomap(np, 0);
43 - arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
44 + arch_ioremap_caller = armada_wa_ioremap_caller;
45
46 /*
47 * We should switch the PL310 to I/O coherency mode only if