target/linux/mvebu/patches-3.10/0175-ARM-mvebu-Relocate-PCIe-node-in-Armada-370-RD-board.patch

   1 From 079d1ecae4bd4166a0f89bcb8e0c96bec1b39622 Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Thu, 8 Aug 2013 18:03:09 -0300
   4 Subject: [PATCH 175/203] ARM: mvebu: Relocate PCIe node in Armada 370 RD board
   5
   6 The pcie-controller node needs to be relocated according the MBus
   7 DT binding, since it's now a child of the mbus-compatible node.
   8
   9 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  10 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
  11 ---
  12  arch/arm/boot/dts/armada-370-rd.dts | 32 ++++++++++++++++----------------
  13  1 file changed, 16 insertions(+), 16 deletions(-)
  14
  15 --- a/arch/arm/boot/dts/armada-370-rd.dts
  16 +++ b/arch/arm/boot/dts/armada-370-rd.dts
  17 @@ -31,6 +31,22 @@
  18                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
  19                           MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
  20
  21 +               pcie-controller {
  22 +                       status = "okay";
  23 +
  24 +                       /* Internal mini-PCIe connector */
  25 +                       pcie@1,0 {
  26 +                               /* Port 0, Lane 0 */
  27 +                               status = "okay";
  28 +                       };
  29 +
  30 +                       /* Internal mini-PCIe connector */
  31 +                       pcie@2,0 {
  32 +                               /* Port 1, Lane 0 */
  33 +                               status = "okay";
  34 +                       };
  35 +               };
  36 +
  37                 internal-regs {
  38                         serial@12000 {
  39                                 clock-frequency = <200000000>;
  40 @@ -88,22 +104,6 @@
  41                                         gpios = <&gpio0 6 1>;
  42                                 };
  43                         };
  44 -
  45 -                       pcie-controller {
  46 -                               status = "okay";
  47 -
  48 -                               /* Internal mini-PCIe connector */
  49 -                               pcie@1,0 {
  50 -                                       /* Port 0, Lane 0 */
  51 -                                       status = "okay";
  52 -                               };
  53 -
  54 -                               /* Internal mini-PCIe connector */
  55 -                               pcie@2,0 {
  56 -                                       /* Port 1, Lane 0 */
  57 -                                       status = "okay";
  58 -                               };
  59 -                       };
  60                 };
  61         };
  62   };