target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9132-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "iEi Puzzle-M902";
  14         compatible = "iei,puzzle-m902",
  15                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  16
  17         chosen {
  18                 stdout-path = "serial0:115200n8";
  19         };
  20
  21         aliases {
  22                 i2c0 = &cp1_i2c0;
  23                 i2c1 = &cp0_i2c0;
  24                 gpio1 = &cp0_gpio1;
  25                 gpio2 = &cp0_gpio2;
  26                 gpio3 = &cp1_gpio1;
  27                 gpio4 = &cp1_gpio2;
  28                 gpio5 = &cp2_gpio1;
  29                 gpio6 = &cp2_gpio2;
  30                 ethernet0 = &cp0_eth0;
  31                 ethernet1 = &cp0_eth1;
  32                 ethernet2 = &cp0_eth2;
  33                 ethernet3 = &cp1_eth0;
  34                 ethernet4 = &cp1_eth1;
  35                 ethernet5 = &cp1_eth2;
  36                 ethernet6 = &cp2_eth0;
  37                 ethernet7 = &cp2_eth1;
  38                 ethernet8 = &cp2_eth2;
  39                 spi1 = &cp0_spi0;
  40                 spi2 = &cp0_spi1;
  41                 led-boot = &led_power;
  42                 led-failsafe = &led_info;
  43                 led-running = &led_power;
  44                 led-upgrade = &led_info;
  45         };
  46
  47         memory@00000000 {
  48                 device_type = "memory";
  49                 reg = <0x0 0x0 0x0 0x80000000>;
  50         };
  51
  52         cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "cp2-xhci0-vbus";
  55                 regulator-min-microvolt = <5000000>;
  56                 regulator-max-microvolt = <5000000>;
  57                 enable-active-high;
  58                 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
  59         };
  60
  61         cp2_usb3_0_phy0: cp2_usb3_phy0 {
  62                 compatible = "usb-nop-xceiv";
  63                 vcc-supply = <&cp2_reg_usb3_vbus0>;
  64         };
  65
  66         cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "cp2-xhci1-vbus";
  69                 regulator-min-microvolt = <5000000>;
  70                 regulator-max-microvolt = <5000000>;
  71                 enable-active-high;
  72                 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
  73         };
  74
  75         cp2_usb3_0_phy1: cp2_usb3_phy1 {
  76                 compatible = "usb-nop-xceiv";
  77                 vcc-supply = <&cp2_reg_usb3_vbus1>;
  78         };
  79
  80         cp2_sfp_eth0: sfp-eth0 {
  81                 compatible = "sff,sfp";
  82                 i2c-bus = <&cp2_sfpp0_i2c>;
  83                 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
  84                 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
  85                 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
  86                 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
  87                 status = "disabled";
  88         };
  89 };
  90
  91 &uart0 {
  92         status = "okay";
  93 };
  94
  95 &cp0_uart0 {
  96         status = "okay";
  97
  98         puzzle-mcu {
  99                 compatible = "iei,wt61p803-puzzle";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 current-speed = <115200>;
 103                 enable-beep;
 104                 status = "okay";
 105
 106                 leds {
 107                         compatible = "iei,wt61p803-puzzle-leds";
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                         status = "okay";
 111
 112                         led@0 {
 113                                 reg = <0>;
 114                                 label = "white:network";
 115                                 active-low;
 116                         };
 117
 118                         led@1 {
 119                                 reg = <1>;
 120                                 label = "green:cloud";
 121                                 active-low;
 122                         };
 123
 124                         led_info: led@2 {
 125                                 reg = <2>;
 126                                 label = "orange:info";
 127                                 active-low;
 128                         };
 129
 130                         led_power: led@3 {
 131                                 reg = <3>;
 132                                 label = "yellow:power";
 133                                 active-low;
 134                                 default-state = "on";
 135                         };
 136                 };
 137
 138                 hwmon {
 139                         compatible = "iei,wt61p803-puzzle-hwmon";
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142
 143                         chassis_fan_group0: fan-group@0 {
 144                                 #cooling-cells = <2>;
 145                                 reg = <0x00>;
 146                                 cooling-levels = <64 102 170 230 250>;
 147                         };
 148                 };
 149         };
 150 };
 151
 152 &ap_thermal_cpu1 {
 153         trips {
 154                 cpu_active: cpu-active {
 155                         temperature = <44000>;
 156                         hysteresis = <2000>;
 157                         type = "active";
 158                 };
 159         };
 160         cooling-maps {
 161                 fan-map {
 162                         trip = <&cpu_active>;
 163                         cooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>;
 164                 };
 165         };
 166 };
 167
 168 /* on-board eMMC - U9 */
 169 &ap_sdhci0 {
 170         pinctrl-names = "default";
 171         bus-width = <8>;
 172         status = "okay";
 173         mmc-ddr-1_8v;
 174         mmc-hs400-1_8v;
 175 };
 176
 177 &cp0_crypto {
 178         status = "okay";
 179 };
 180
 181 &cp0_xmdio {
 182         status = "okay";
 183         cp0_nbaset_phy0: ethernet-phy@0 {
 184                 compatible = "ethernet-phy-ieee802.3-c45";
 185                 reg = <2>;
 186         };
 187         cp0_nbaset_phy1: ethernet-phy@1 {
 188                 compatible = "ethernet-phy-ieee802.3-c45";
 189                 reg = <0>;
 190         };
 191         cp0_nbaset_phy2: ethernet-phy@2 {
 192                 compatible = "ethernet-phy-ieee802.3-c45";
 193                 reg = <8>;
 194         };
 195 };
 196
 197 &cp0_ethernet {
 198         status = "okay";
 199 };
 200
 201 /* SLM-1521-V2, CON9 */
 202 &cp0_eth0 {
 203         status = "okay";
 204         phy-mode = "10gbase-kr";
 205         phys = <&cp0_comphy2 0>;
 206         managed = "in-band-status";
 207 };
 208
 209 &cp0_eth1 {
 210         status = "okay";
 211         phy-mode = "2500base-x";
 212         phys = <&cp0_comphy4 1>;
 213         managed = "in-band-status";
 214 };
 215
 216 &cp0_eth2 {
 217         status = "okay";
 218         phy-mode = "2500base-x";
 219         phys = <&cp0_comphy1 2>;
 220         managed = "in-band-status";
 221 };
 222
 223 &cp0_gpio1 {
 224         status = "okay";
 225 };
 226
 227 &cp0_gpio2 {
 228         status = "okay";
 229 };
 230
 231 &cp0_i2c0 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&cp0_i2c0_pins>;
 234         status = "okay";
 235         clock-frequency = <100000>;
 236         rtc@32 {
 237                 compatible = "epson,rx8130";
 238                 reg = <0x32>;
 239                 wakeup-source;
 240         };
 241 };
 242
 243 &cp0_i2c1 {
 244         clock-frequency = <100000>;
 245 };
 246
 247 /* SLM-1521-V2, CON6 */
 248 &cp0_sata0 {
 249         status = "okay";
 250         sata-port@1 {
 251                 status = "okay";
 252                 phys = <&cp0_comphy0 1>;
 253         };
 254 };
 255
 256 &cp0_pcie2 {
 257         status = "okay";
 258         num-lanes = <1>;
 259         num-viewport = <8>;
 260         phys = <&cp0_comphy5 2>;
 261 };
 262
 263 /* U55 */
 264 &cp0_spi1 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&cp0_spi0_pins>;
 267         reg = <0x700680 0x50>,          /* control */
 268               <0x2000000 0x1000000>;    /* CS0 */
 269         status = "okay";
 270         spi-flash@0 {
 271                 #address-cells = <0x1>;
 272                 #size-cells = <0x1>;
 273                 compatible = "jedec,spi-nor";
 274                 reg = <0x0>;
 275                 spi-max-frequency = <40000000>;
 276                 partitions {
 277                         compatible = "fixed-partitions";
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         partition@0 {
 281                                 label = "U-Boot";
 282                                 reg = <0x0 0x1f0000>;
 283                         };
 284                         partition@1f0000 {
 285                                 label = "U-Boot ENV Factory";
 286                                 reg = <0x1f0000 0x10000>;
 287                         };
 288                         partition@200000 {
 289                                 label = "Reserved";
 290                                 reg = <0x200000 0x1f0000>;
 291                         };
 292                         partition@3f0000 {
 293                                 label = "U-Boot ENV";
 294                                 reg = <0x3f0000 0x10000>;
 295                         };
 296                 };
 297         };
 298 };
 299
 300 &cp0_syscon0 {
 301         cp0_pinctrl: pinctrl {
 302                 compatible = "marvell,cp115-standalone-pinctrl";
 303                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 304                         marvell,pins = "mpp37", "mpp38";
 305                         marvell,function = "i2c0";
 306                 };
 307                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 308                         marvell,pins = "mpp35", "mpp36";
 309                         marvell,function = "i2c1";
 310                 };
 311                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 312                         marvell,pins = "mpp0", "mpp1", "mpp2",
 313                                        "mpp3", "mpp4", "mpp5",
 314                                        "mpp6", "mpp7", "mpp8",
 315                                        "mpp9", "mpp10", "mpp11";
 316                         marvell,function = "ge0";
 317                 };
 318                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 319                         marvell,pins = "mpp44", "mpp45", "mpp46",
 320                                        "mpp47", "mpp48", "mpp49",
 321                                        "mpp50", "mpp51", "mpp52",
 322                                        "mpp53", "mpp54", "mpp55";
 323                         marvell,function = "ge1";
 324                 };
 325                 cp0_spi0_pins: cp0-spi-pins-0 {
 326                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 327                         marvell,function = "spi1";
 328                 };
 329         };
 330 };
 331
 332 &cp0_usb3_1 {
 333         status = "okay";
 334         phys = <&cp0_comphy3 1>;
 335         phy-names = "usb";
 336 };
 337
 338 /*
 339  * Instantiate the first connected CP115
 340  */
 341
 342 #define CP11X_NAME              cp1
 343 #define CP11X_BASE              f4000000
 344 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 345 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 346 #define CP11X_PCIE0_BASE        f4600000
 347 #define CP11X_PCIE1_BASE        f4620000
 348 #define CP11X_PCIE2_BASE        f4640000
 349
 350 #include "armada-cp115.dtsi"
 351
 352 #undef CP11X_NAME
 353 #undef CP11X_BASE
 354 #undef CP11X_PCIEx_MEM_BASE
 355 #undef CP11X_PCIEx_MEM_SIZE
 356 #undef CP11X_PCIE0_BASE
 357 #undef CP11X_PCIE1_BASE
 358 #undef CP11X_PCIE2_BASE
 359
 360 &cp1_crypto {
 361         status = "okay";
 362 };
 363
 364 &cp1_xmdio {
 365         status = "okay";
 366         cp1_nbaset_phy0: ethernet-phy@3 {
 367                 compatible = "ethernet-phy-ieee802.3-c45";
 368                 reg = <2>;
 369         };
 370         cp1_nbaset_phy1: ethernet-phy@4 {
 371                 compatible = "ethernet-phy-ieee802.3-c45";
 372                 reg = <0>;
 373         };
 374         cp1_nbaset_phy2: ethernet-phy@5 {
 375                 compatible = "ethernet-phy-ieee802.3-c45";
 376                 reg = <8>;
 377         };
 378 };
 379
 380 &cp1_ethernet {
 381         status = "okay";
 382 };
 383
 384 /* CON50 */
 385 &cp1_eth0 {
 386         status = "okay";
 387         phy-mode = "10gbase-kr";
 388         phys = <&cp1_comphy2 0>;
 389         managed = "in-band-status";
 390 };
 391
 392 &cp1_eth1 {
 393         status = "okay";
 394         phy-mode = "2500base-x";
 395         phys = <&cp1_comphy4 1>;
 396         managed = "in-band-status";
 397 };
 398
 399 &cp1_eth2 {
 400         status = "okay";
 401         phy-mode = "2500base-x";
 402         phys = <&cp1_comphy1 2>;
 403         managed = "in-band-status";
 404 };
 405
 406 &cp1_gpio1 {
 407         status = "okay";
 408 };
 409
 410 &cp1_gpio2 {
 411         status = "okay";
 412 };
 413
 414 &cp1_i2c0 {
 415         status = "okay";
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&cp1_i2c0_pins>;
 418         clock-frequency = <100000>;
 419 };
 420
 421 &cp1_syscon0 {
 422         cp1_pinctrl: pinctrl {
 423                 compatible = "marvell,cp115-standalone-pinctrl";
 424                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 425                         marvell,pins = "mpp37", "mpp38";
 426                         marvell,function = "i2c0";
 427                 };
 428                 cp1_spi0_pins: cp1-spi-pins-0 {
 429                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 430                         marvell,function = "spi1";
 431                 };
 432                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 433                         marvell,pins = "mpp3";
 434                         marvell,function = "gpio";
 435                 };
 436         };
 437 };
 438
 439 /*
 440  * Instantiate the second connected CP115
 441  */
 442
 443 #define CP11X_NAME              cp2
 444 #define CP11X_BASE              f6000000
 445 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
 446 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 447 #define CP11X_PCIE0_BASE        f6600000
 448 #define CP11X_PCIE1_BASE        f6620000
 449 #define CP11X_PCIE2_BASE        f6640000
 450
 451 #include "armada-cp115.dtsi"
 452
 453 #undef CP11X_NAME
 454 #undef CP11X_BASE
 455 #undef CP11X_PCIEx_MEM_BASE
 456 #undef CP11X_PCIEx_MEM_SIZE
 457 #undef CP11X_PCIE0_BASE
 458 #undef CP11X_PCIE1_BASE
 459 #undef CP11X_PCIE2_BASE
 460
 461 &cp2_crypto {
 462         status = "okay";
 463 };
 464
 465 &cp2_ethernet {
 466         status = "okay";
 467 };
 468
 469 &cp2_xmdio {
 470         status = "okay";
 471         cp2_nbaset_phy0: ethernet-phy@6 {
 472                 compatible = "ethernet-phy-ieee802.3-c45";
 473                 reg = <2>;
 474         };
 475         cp2_nbaset_phy1: ethernet-phy@7 {
 476                 compatible = "ethernet-phy-ieee802.3-c45";
 477                 reg = <0>;
 478         };
 479         cp2_nbaset_phy2: ethernet-phy@8 {
 480                 compatible = "ethernet-phy-ieee802.3-c45";
 481                 reg = <8>;
 482         };
 483 };
 484
 485 /* SLM-1521-V2, CON9 */
 486 &cp2_eth0 {
 487         status = "okay";
 488         phy-mode = "10gbase-kr";
 489         phys = <&cp2_comphy2 0>;
 490         managed = "in-band-status";
 491 };
 492
 493 &cp2_eth1 {
 494         status = "okay";
 495         phy-mode = "2500base-x";
 496         phys = <&cp2_comphy4 1>;
 497         managed = "in-band-status";
 498 };
 499
 500 &cp2_eth2 {
 501         status = "okay";
 502         phy-mode = "2500base-x";
 503         phys = <&cp2_comphy1 2>;
 504         managed = "in-band-status";
 505 };
 506
 507 &cp2_gpio1 {
 508         status = "okay";
 509 };
 510
 511 &cp2_gpio2 {
 512         status = "okay";
 513 };
 514
 515 &cp2_i2c0 {
 516         clock-frequency = <100000>;
 517         /* SLM-1521-V2 - U3 */
 518         i2c-mux@72 {
 519                 compatible = "nxp,pca9544";
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 reg = <0x72>;
 523                 cp2_sfpp0_i2c: i2c@0 {
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         reg = <0>;
 527                 };
 528
 529                 i2c@1 {
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         reg = <1>;
 533                         /* U12 */
 534                         cp2_module_expander1: pca9555@21 {
 535                                 compatible = "nxp,pca9555";
 536                                 pinctrl-names = "default";
 537                                 gpio-controller;
 538                                 #gpio-cells = <2>;
 539                                 reg = <0x21>;
 540                         };
 541                 };
 542         };
 543 };
 544
 545 &cp2_syscon0 {
 546         cp2_pinctrl: pinctrl {
 547                 compatible = "marvell,cp115-standalone-pinctrl";
 548                 cp2_i2c0_pins: cp2-i2c-pins-0 {
 549                         marvell,pins = "mpp37", "mpp38";
 550                         marvell,function = "i2c0";
 551                 };
 552         };
 553 };