target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "armada-385-fortinet-fg-x0e.dtsi"
   4
   5 / {
   6         model = "Fortinet FortiGate 50E";
   7         compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
   8
   9         memory@0 {
  10                 device_type = "memory";
  11                 reg = <0x00000000 0x80000000>; /* 2GB */
  12         };
  13 };
  14
  15 &gpio_leds {
  16         led-14 {
  17                 label = "green:speed_wan1";
  18                 gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
  19                 color = <LED_COLOR_ID_GREEN>;
  20                 linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
  21         };
  22
  23         led-15 {
  24                 label = "green:speed_wan2";
  25                 gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  26                 color = <LED_COLOR_ID_GREEN>;
  27                 linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
  28         };
  29
  30         led-16 {
  31                 label = "amber:speed_lan5";
  32                 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
  33                 color = <LED_COLOR_ID_AMBER>;
  34                 linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
  35         };
  36
  37         led-17 {
  38                 label = "green:speed_lan5";
  39                 gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
  40                 color = <LED_COLOR_ID_GREEN>;
  41                 linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
  42         };
  43 };
  44
  45 &pinctrl {
  46         pmx_phy_switch_pins: phy-switch-pins {
  47                 marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
  48                 marvell,function = "gpio";
  49         };
  50 };
  51
  52 &eth1 {
  53         status = "okay";
  54
  55         phy-handle = <&ethphy0>;
  56         phy-connection-type = "sgmii";
  57         buffer-manager = <&bm>;
  58         bm,pool-long = <2>;
  59         nvmem-cells = <&macaddr_bdinfo_d880 1>;
  60         nvmem-cell-names = "mac-address";
  61 };
  62
  63 &eth2 {
  64         status = "okay";
  65
  66         phy-handle = <&ethphy1>;
  67         phy-connection-type = "sgmii";
  68         buffer-manager = <&bm>;
  69         bm,pool-long = <3>;
  70         nvmem-cells = <&macaddr_bdinfo_d880 2>;
  71         nvmem-cell-names = "mac-address";
  72 };
  73
  74 &mdio {
  75         pinctrl-names = "default";
  76         pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
  77
  78         /* Marvell 88E1512 */
  79         ethphy0: ethernet-phy@0 {
  80                 compatible = "ethernet-phy-id0141,0dd1",
  81                              "ethernet-phy-ieee802.3-c22";
  82                 reg = <0>;
  83                 interrupt-parent = <&gpio0>;
  84                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
  85                 reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
  86                 reset-assert-us = <10000>;
  87                 reset-deassert-us = <10000>;
  88                 /*
  89                  * LINK/ACT   (Green): LED[0], Active Low
  90                  * SPEED 100M (Amber): LED[1], Active High
  91                  */
  92                 marvell,reg-init = <3 16 0 0x71>,
  93                                    <3 17 0 0x4>;
  94         };
  95
  96         /* Marvell 88E1512 */
  97         ethphy1: ethernet-phy@1 {
  98                 compatible = "ethernet-phy-id0141,0dd1",
  99                              "ethernet-phy-ieee802.3-c22";
 100                 reg = <1>;
 101                 interrupt-parent = <&gpio1>;
 102                 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
 103                 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 104                 reset-assert-us = <10000>;
 105                 reset-deassert-us = <10000>;
 106                 /*
 107                  * LINK/ACT   (Green): LED[0], Active Low
 108                  * SPEED 100M (Amber): LED[1], Active High
 109                  */
 110                 marvell,reg-init = <3 16 0 0x71>,
 111                                    <3 17 0 0x4>;
 112         };
 113
 114         /* Marvell 88E6176 */
 115         switch@2 {
 116                 compatible = "marvell,mv88e6085";
 117                 reg = <0x2>;
 118                 reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
 119
 120                 ports {
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123
 124                         port@0 {
 125                                 reg = <0>;
 126                                 label = "lan5";
 127                                 nvmem-cells = <&macaddr_bdinfo_d880 7>;
 128                                 nvmem-cell-names = "mac-address";
 129                         };
 130
 131                         port@1 {
 132                                 reg = <1>;
 133                                 label = "lan4";
 134                                 nvmem-cells = <&macaddr_bdinfo_d880 6>;
 135                                 nvmem-cell-names = "mac-address";
 136                         };
 137
 138                         port@2 {
 139                                 reg = <2>;
 140                                 label = "lan3";
 141                                 nvmem-cells = <&macaddr_bdinfo_d880 5>;
 142                                 nvmem-cell-names = "mac-address";
 143                         };
 144
 145                         port@3 {
 146                                 reg = <3>;
 147                                 label = "lan2";
 148                                 nvmem-cells = <&macaddr_bdinfo_d880 4>;
 149                                 nvmem-cell-names = "mac-address";
 150                         };
 151
 152                         port@4 {
 153                                 reg = <4>;
 154                                 label = "lan1";
 155                                 nvmem-cells = <&macaddr_bdinfo_d880 3>;
 156                                 nvmem-cell-names = "mac-address";
 157                         };
 158
 159                         port@6 {
 160                                 reg = <6>;
 161                                 ethernet = <&eth0>;
 162                                 phy-connection-type = "rgmii-id";
 163
 164                                 fixed-link {
 165                                         speed = <1000>;
 166                                         full-duplex;
 167                                 };
 168                         };
 169                 };
 170         };
 171 };