5d214e38a4e9681dfbe8a2f379b8b29c0cd22c37
[openwrt/staging/stintel.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / ws-ap3715i.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later or MIT
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6
7 /include/ "fsl/p1010si-pre.dtsi"
8
9 / {
10 model = "Enterasys WS-AP3715i";
11 compatible = "enterasys,ws-ap3715i";
12
13 aliases {
14 led-boot = &led_power_green;
15 led-failsafe = &led_power_red;
16 led-running = &led_power_green;
17 led-upgrade = &led_power_red;
18 };
19
20 chosen {
21 bootargs = "console=ttyS0,115200";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x0 0x0 0x0 0x10000000>;
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 wifi1 {
33 gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
34 label = "green:radio1";
35 linux,default-trigger = "phy1tpt";
36 };
37
38 wifi2 {
39 gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
40 label = "green:radio2";
41 linux,default-trigger = "phy0tpt";
42 };
43
44 led_power_green: power_green {
45 gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
46 function = LED_FUNCTION_POWER;
47 color = <LED_COLOR_ID_GREEN>;
48 };
49
50 led_power_red: power_red {
51 gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
52 function = LED_FUNCTION_POWER;
53 color = <LED_COLOR_ID_RED>;
54 };
55
56 lan1_red {
57 gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
58 label = "red:lan1";
59 };
60
61 lan1_green {
62 gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
63 label = "green:lan1";
64 };
65
66 lan2_red {
67 gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
68 label = "red:lan2";
69 };
70
71 lan2_green {
72 gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
73 label = "green:lan2";
74 };
75 };
76
77 keys {
78 compatible = "gpio-keys";
79
80 reset {
81 label = "Reset button";
82 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
83 linux,code = <KEY_RESTART>;
84 };
85 };
86
87 soc: soc@ffe00000 {
88 ranges = <0x0 0x0 0xffe00000 0x100000>;
89
90 gpio0: gpio-controller@fc00 {
91 };
92
93 usb@22000 {
94 status = "disabled";
95 };
96
97 mdio@24000 {
98 phy0: ethernet-phy@0 {
99 reg = <0x1>;
100 };
101
102 phy2: ethernet-phy@2 {
103 reg = <0x2>;
104 };
105 };
106
107 mdio@25000 {
108 tbi_phy: tbi-phy@11 {
109 reg = <0x11>;
110 };
111 };
112
113 mdio@26000 {
114 status = "disabled";
115 };
116
117 enet0: ethernet@b0000 {
118 phy-handle = <&phy0>;
119 phy-connection-type = "rgmii-id";
120
121 label = "lan1";
122 };
123
124 enet1: ethernet@b1000 {
125 phy-handle = <&phy2>;
126 phy-connection-type = "sgmii";
127
128 tbi-handle = <&tbi_phy>;
129
130 label = "lan2";
131 };
132
133 enet2: ethernet@b2000 {
134 status = "disabled";
135 };
136
137 sdhc@2e000 {
138 status = "disabled";
139 };
140 };
141
142 ifc: ifc@ffe1e000 {
143 };
144
145 pci0: pcie@ffe09000 {
146 reg = <0 0xffe09000 0 0x1000>;
147 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
148 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
149 pcie@0 {
150 ranges = <0x2000000 0x0 0xa0000000
151 0x2000000 0x0 0xa0000000
152 0x0 0x20000000
153
154 0x1000000 0x0 0x0
155 0x1000000 0x0 0x0
156 0x0 0x100000>;
157
158 wifi@0,0 {
159 compatible = "pci168c,0033";
160 reg = <0x0 0 0 0 0>;
161 ieee80211-freq-limit = <2400000 2500000>;
162 };
163 };
164 };
165
166 pci1: pcie@ffe0a000 {
167 reg = <0 0xffe0a000 0 0x1000>;
168 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
169 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
170 pcie@0 {
171 ranges = <0x2000000 0x0 0x80000000
172 0x2000000 0x0 0x80000000
173 0x0 0x20000000
174
175 0x1000000 0x0 0x0
176 0x1000000 0x0 0x0
177 0x0 0x100000>;
178
179 wifi@0,0 {
180 compatible = "pci168c,0033";
181 reg = <0x0 0 0 0 0>;
182 ieee80211-freq-limit = <5000000 6000000>;
183 };
184 };
185 };
186 };
187
188 &soc {
189 led_spi {
190 compatible = "spi-gpio";
191 #address-cells = <1>;
192 #size-cells = <0>;
193
194 sck-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
195 mosi-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
196 num-chipselects = <0>;
197
198 spi_gpio: led_gpio@0 {
199 compatible = "fairchild,74hc595";
200 reg = <0>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 registers-number = <1>;
204 spi-max-frequency = <100000>;
205 };
206 };
207
208 spi0: spi@7000 {
209 flash@0 {
210 compatible = "jedec,spi-nor";
211 reg = <0>;
212 spi-max-frequency = <25000000>;
213
214 partitions {
215 compatible = "fixed-partitions";
216 #address-cells = <1>;
217 #size-cells = <1>;
218
219 partition@0 {
220 reg = <0x0 0xa0000>;
221 label = "boot-bak";
222 read-only;
223 };
224
225 partition@a0000 {
226 reg = <0xa0000 0xa0000>;
227 label = "boot-pri";
228 read-only;
229 };
230
231 partition@120000 {
232 reg = <0x120000 0x10000>;
233 label = "cfg1";
234 read-only;
235 };
236
237 partition@130000 {
238 reg = <0x130000 0x10000>;
239 label = "cfg2";
240 read-only;
241 };
242
243 partition@140000 {
244 compatible = "denx,uimage";
245 reg = <0x140000 0x1d80000>;
246 label = "firmware";
247 };
248
249 partition@1ec0000 {
250 reg = <0x1ec0000 0x100000>;
251 label = "nvram";
252 read-only;
253 };
254 };
255 };
256 };
257 };
258
259 /include/ "fsl/p1010si-post.dtsi"
260
261 / {
262 cpus {
263 PowerPC,P1010@0 {
264 bus-frequency = <399999996>;
265 timebase-frequency = <50000000>;
266 clock-frequency = <799999992>;
267 d-cache-block-size = <0x20>;
268 d-cache-size = <0x8000>;
269 d-cache-sets = <0x80>;
270 i-cache-block-size = <0x20>;
271 i-cache-size = <0x8000>;
272 i-cache-sets = <0x80>;
273 };
274 };
275
276 soc@ffe00000 {
277 bus-frequency = <399999996>;
278
279 serial@4600 {
280 clock-frequency = <399999996>;
281 status = "disabled";
282 };
283
284 serial@4500 {
285 clock-frequency = <399999996>;
286 };
287
288 pic@40000 {
289 clock-frequency = <399999996>;
290 };
291 };
292 };
293
294 /*
295 * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
296 * aliases to determine PCI domain numbers, drop aliases so as not to
297 * change the sysfs path of our wireless netdevs.
298 */
299
300 / {
301 aliases {
302 /delete-property/ pci0;
303 /delete-property/ pci1;
304 };
305 };
306