mpc85xx: drop redundant label with new LED color/function format
[openwrt/staging/nbd.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / br200-wp.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Aerohive BR200-WP Device Tree Source
4 *
5 * Based on: Aerohive HiveAP-330 Device Tree Source
6 *
7 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
8 * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
9 */
10
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/gpio.h>
14
15 /include/ "fsl/p1020si-pre.dtsi"
16
17 / {
18 model = "Aerohive BR200-WP";
19 compatible = "aerohive,br200-wp";
20
21 chosen {
22 bootargs = "console=ttyS0,9600";
23 bootargs-override = "console=ttyS0,9600 noinitrd";
24 };
25
26 aliases {
27 led-boot = &led_attention;
28 led-failsafe = &led_attention;
29 led-running = &led_status;
30 led-upgrade = &led_status;
31 label-mac-device = &enet0;
32 };
33
34 memory {
35 device_type = "memory";
36 };
37
38 cpus {
39 /delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
40 };
41
42 board_lbc: lbc: localbus@ffe05000 {
43 reg = <0 0xffe05000 0 0x1000>;
44 ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
45
46 nor@0 {
47 compatible = "cfi-flash";
48 reg = <0x0 0x0 0x4000000>;
49 bank-width = <2>;
50 device-width = <1>;
51
52 partitions {
53 compatible = "fixed-partitions";
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 partition@0 {
58 reg = <0x0 0x40000>;
59 label = "dtb";
60 };
61
62 partition@40000 {
63 reg = <0x40000 0x40000>;
64 label = "initramfs";
65 };
66
67 partition@80000 {
68 reg = <0x80000 0x27c0000>;
69 label = "rootfs";
70 };
71
72 partition@2840000 {
73 reg = <0x2840000 0x800000>;
74 label = "kernel";
75 };
76
77 partition@3040000 {
78 reg = <0x3040000 0xec0000>;
79 label = "stock-jffs2";
80 read-only;
81 };
82
83 partition@3f00000 {
84 reg = <0x3f00000 0x20000>;
85 label = "hw-info";
86 read-only;
87
88 nvmem-layout {
89 compatible = "fixed-layout";
90 #address-cells = <1>;
91 #size-cells = <1>;
92
93 macaddr_hwinfo_0: macaddr@0 {
94 compatible = "mac-base";
95 reg = <0x0 0x6>;
96 #nvmem-cell-cells = <1>;
97 };
98 };
99 };
100
101 partition@3f20000 {
102 reg = <0x3f20000 0x20000>;
103 label = "boot-info";
104 read-only;
105 };
106
107 partition@3f40000 {
108 reg = <0x3f40000 0x20000>;
109 label = "boot-info-backup";
110 read-only;
111 };
112
113 partition@3f60000 {
114 reg = <0x3f60000 0x20000>;
115 label = "u-boot-env";
116 };
117
118 partition@3f80000 {
119 reg = <0x3f80000 0x80000>;
120 label = "u-boot";
121 read-only;
122 };
123
124 firmware@0 {
125 reg = <0x0 0x3040000>;
126 label = "firmware";
127 };
128 };
129 };
130 };
131
132 board_soc: soc: soc@ffe00000 {
133 ranges = <0x0 0x0 0xffe00000 0x100000>;
134
135 mdio@24000 {
136
137 phy_port1: phy@0 {
138 reg = <0>;
139 };
140
141 phy_port2: phy@1 {
142 reg = <1>;
143 };
144
145 phy_port3: phy@2 {
146 reg = <2>;
147 };
148
149 phy_port4: phy@3 {
150 reg = <3>;
151 };
152
153 phy_port5: phy@4 {
154 reg = <4>;
155 };
156
157 switch@10 {
158 compatible = "qca,qca8327";
159 reg = <0x10>;
160 reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
161
162 ports {
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 port@1 {
167 reg = <1>;
168 label = "lan1";
169 phy-handle = <&phy_port1>;
170 nvmem-cells = <&macaddr_hwinfo_0 2>;
171 nvmem-cell-names = "mac-address";
172 };
173
174 port@2 {
175 reg = <2>;
176 label = "lan2";
177 phy-handle = <&phy_port2>;
178 nvmem-cells = <&macaddr_hwinfo_0 3>;
179 nvmem-cell-names = "mac-address";
180 };
181
182 port@3 {
183 reg = <3>;
184 label = "lan3";
185 phy-handle = <&phy_port3>;
186 nvmem-cells = <&macaddr_hwinfo_0 4>;
187 nvmem-cell-names = "mac-address";
188 };
189
190 port@4 {
191 reg = <4>;
192 label = "lan4";
193 phy-handle = <&phy_port4>;
194 nvmem-cells = <&macaddr_hwinfo_0 5>;
195 nvmem-cell-names = "mac-address";
196 };
197
198 port@5 {
199 reg = <5>;
200 label = "wan";
201 phy-handle = <&phy_port5>;
202 nvmem-cells = <&macaddr_hwinfo_0 0>;
203 nvmem-cell-names = "mac-address";
204 };
205
206 port@6 {
207 reg = <6>;
208 ethernet = <&enet0>;
209 phy-mode = "rgmii-id";
210
211 fixed-link {
212 speed = <1000>;
213 full-duplex;
214 };
215 };
216 };
217 };
218 };
219
220 mdio@25000 {
221 status = "disabled";
222 };
223
224 mdio@26000 {
225 status = "disabled";
226 };
227
228 enet0: ethernet@b0000 {
229 status = "okay";
230 phy-connection-type = "rgmii-id";
231 nvmem-cells = <&macaddr_hwinfo_0 0>;
232 nvmem-cell-names = "mac-address";
233
234 fixed-link {
235 speed = <1000>;
236 full-duplex;
237 };
238 };
239
240 enet1: ethernet@b1000 {
241 status = "disabled";
242 };
243
244 enet2: ethernet@b2000 {
245 status = "disabled";
246 };
247
248 gpio0: gpio-controller@fc00 {
249 };
250
251 usb@22000 {
252 phy_type = "ulpi";
253 dr_mode = "host";
254 };
255
256 usb@23000 {
257 status = "disabled";
258 };
259 };
260
261 pci0: pcie@ffe09000 {
262 status = "disabled";
263 };
264
265 pci1: pcie@ffe0a000 {
266 reg = <0x0 0xffe0a000 0x0 0x1000>;
267 ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
268 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
269
270 reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
271
272 pcie@0 {
273 ranges = <0x2000000 0x0 0xc0000000
274 0x2000000 0x0 0xc0000000
275 0x0 0x20000000
276
277 0x1000000 0x0 0x0
278 0x1000000 0x0 0x0
279 0x0 0x100000>;
280
281 ath9k: wifi@0,0 {
282 reg = <0x0000 0 0 0 0>;
283 #gpio-cells = <2>;
284 gpio-controller;
285 nvmem-cells = <&macaddr_hwinfo_0 16>;
286 nvmem-cell-names = "mac-address";
287 };
288 };
289 };
290
291 leds {
292 compatible = "gpio-leds";
293
294 led_attention: led-0 {
295 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
296 color = <LED_COLOR_ID_AMBER>;
297 function = LED_FUNCTION_STATUS;
298 };
299
300 led_status: led-1 {
301 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
302 color = <LED_COLOR_ID_WHITE>;
303 function = LED_FUNCTION_STATUS;
304 };
305 };
306
307 buttons {
308 compatible = "gpio-keys";
309
310 reset {
311 label = "Reset button";
312 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
313 linux,code = <KEY_RESTART>;
314 };
315 };
316 };
317
318 /include/ "fsl/p1020si-post.dtsi"
319
320 / {
321 chosen {
322 stdout-path = "/soc@ffe00000/serial@4500";
323 };
324
325 cpus {
326 PowerPC,P1020@0 {
327 i-cache-sets = <0x80>;
328 i-cache-size = <0x8000>;
329 i-cache-block-size = <0x20>;
330 d-cache-sets = <0x80>;
331 d-cache-size = <0x8000>;
332 d-cache-block-size = <0x20>;
333 clock-frequency = <0x2756cd00>;
334 bus-frequency = <0x13ab6680>;
335 timebase-frequency = <0x2756cd0>;
336 };
337 };
338
339 memory {
340 reg = <0x00 0x00 0x00 0x10000000>;
341 };
342
343 localbus@ffe05000 {
344 bus-frequency = <0x13ab668>;
345 };
346
347 soc@ffe00000 {
348 bus-frequency = <0x13ab6680>;
349
350 serial@4500 {
351 clock-frequency = <0x13ab6680>;
352 };
353
354 serial@4600 {
355 clock-frequency = <0x13ab6680>;
356 };
357 };
358
359 pcie@ffe09000 {
360 clock-frequency = <0x1fca055>;
361 };
362
363 pcie@ffe0a000 {
364 clock-frequency = <0x1fca055>;
365 };
366 };