target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Fri, 4 Sep 2020 18:36:06 +0200
   3 Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent DMA
   4
   5 It improves performance by eliminating the need for a cache flush on rx and tx
   6
   7 Signed-off-by: Felix Fietkau <nbd@nbd.name>
   8 ---
   9
  10 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  11 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  12 @@ -357,7 +357,7 @@
  13                 };
  14
  15                 cci_control2: slave-if@5000 {
  16 -                       compatible = "arm,cci-400-ctrl-if";
  17 +                       compatible = "arm,cci-400-ctrl-if", "syscon";
  18                         interface-type = "ace";
  19                         reg = <0x5000 0x1000>;
  20                 };
  21 @@ -967,6 +967,8 @@
  22                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
  23                 mediatek,ethsys = <&ethsys>;
  24                 mediatek,sgmiisys = <&sgmiisys>;
  25 +               mediatek,cci-control = <&cci_control2>;
  26 +               dma-coherent;
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29                 status = "disabled";
  30 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  31 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  32 @@ -9,6 +9,7 @@
  33  #include <linux/of_device.h>
  34  #include <linux/of_mdio.h>
  35  #include <linux/of_net.h>
  36 +#include <linux/of_address.h>
  37  #include <linux/mfd/syscon.h>
  38  #include <linux/regmap.h>
  39  #include <linux/clk.h>
  40 @@ -2486,6 +2487,12 @@ static int mtk_hw_init(struct mtk_eth *e
  41         if (ret)
  42                 goto err_disable_pm;
  43
  44 +       if (of_dma_is_coherent(eth->dev->of_node)) {
  45 +               u32 mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA;
  46 +
  47 +               regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, mask, mask);
  48 +       }
  49 +
  50         if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
  51                 ret = device_reset(eth->dev);
  52                 if (ret) {
  53 @@ -3088,6 +3095,16 @@ static int mtk_probe(struct platform_dev
  54                 }
  55         }
  56
  57 +       if (of_dma_is_coherent(pdev->dev.of_node)) {
  58 +               struct regmap *cci;
  59 +
  60 +               cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  61 +                                                     "mediatek,cci-control");
  62 +               /* enable CPU/bus coherency */
  63 +               if (!IS_ERR(cci))
  64 +                       regmap_write(cci, 0, 3);
  65 +       }
  66 +
  67         if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
  68                 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
  69                                           GFP_KERNEL);
  70 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  71 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  72 @@ -426,6 +426,11 @@
  73  #define RSTCTRL_FE             BIT(6)
  74  #define RSTCTRL_PPE            BIT(31)
  75
  76 +/* ethernet dma channel agent map */
  77 +#define ETHSYS_DMA_AG_MAP      0x408
  78 +#define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
  79 +#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
  80 +
  81  /* SGMII subsystem config registers */
  82  /* Register to auto-negotiation restart */
  83  #define SGMSYS_PCS_CONTROL_1   0x0