target/linux/mediatek/patches-4.14/0227-arm-dts-Add-Unielec-U7623-DTS.patch

   1 From 13872b8abfadfe70598c065c19d1db759477c4e6 Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Sun, 17 Jun 2018 14:41:47 +0200
   4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
   5
   6 ---
   7  arch/arm/boot/dts/Makefile                         |   1 +
   8  .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts     |  17 +
   9  .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi    | 375 +++++++++++++++++++++
  10  3 files changed, 393 insertions(+)
  11  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  12  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  13
  14 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
  15 index 3fec84fa0..e685ce9a4 100644
  16 --- a/arch/arm/boot/dts/Makefile
  17 +++ b/arch/arm/boot/dts/Makefile
  18 @@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  19         mt6589-aquaris5.dtb \
  20         mt6592-evb.dtb \
  21         mt7623a-rfb-emmc.dtb \
  22 +       mt7623a-unielec-u7623-02-emmc-512M.dtb \
  23         mt7623n-rfb-nand.dtb \
  24         mt7623n-bananapi-bpi-r2.dtb \
  25         mt8127-moose.dtb \
  26 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  27 new file mode 100644
  28 index 000000000..3b14eccd3
  29 --- /dev/null
  30 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  31 @@ -0,0 +1,17 @@
  32 +/*
  33 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  34 + *
  35 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  36 + */
  37 +
  38 +/dts-v1/;
  39 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
  40 +
  41 +/ {
  42 +       model = "UniElec U7623-02 eMMC (512M RAM)";
  43 +       compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
  44 +
  45 +       memory {
  46 +               reg = <0 0x80000000 0 0x20000000>;
  47 +       };
  48 +};
  49 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  50 new file mode 100644
  51 index 000000000..436b02f2d
  52 --- /dev/null
  53 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  54 @@ -0,0 +1,375 @@
  55 +/*
  56 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  57 + *
  58 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  59 + */
  60 +
  61 +#include <dt-bindings/input/input.h>
  62 +#include "mt7623.dtsi"
  63 +#include "mt6323.dtsi"
  64 +
  65 +/ {
  66 +       compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
  67 +
  68 +       aliases {
  69 +               serial2 = &uart2;
  70 +       };
  71 +
  72 +       chosen {
  73 +               bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
  74 +               stdout-path = "serial2:115200n8";
  75 +       };
  76 +
  77 +       memory {
  78 +               reg = <0 0x80000000 0 0x20000000>;
  79 +       };
  80 +
  81 +       cpus {
  82 +               cpu@0 {
  83 +                       proc-supply = <&mt6323_vproc_reg>;
  84 +               };
  85 +
  86 +               cpu@1 {
  87 +                       proc-supply = <&mt6323_vproc_reg>;
  88 +               };
  89 +
  90 +               cpu@2 {
  91 +                       proc-supply = <&mt6323_vproc_reg>;
  92 +               };
  93 +
  94 +               cpu@3 {
  95 +                       proc-supply = <&mt6323_vproc_reg>;
  96 +               };
  97 +       };
  98 +
  99 +       reg_1p8v: regulator-1p8v {
 100 +               compatible = "regulator-fixed";
 101 +               regulator-name = "fixed-1.8V";
 102 +               regulator-min-microvolt = <1800000>;
 103 +               regulator-max-microvolt = <1800000>;
 104 +               regulator-boot-on;
 105 +               regulator-always-on;
 106 +       };
 107 +
 108 +       reg_3p3v: regulator-3p3v {
 109 +               compatible = "regulator-fixed";
 110 +               regulator-name = "fixed-3.3V";
 111 +               regulator-min-microvolt = <3300000>;
 112 +               regulator-max-microvolt = <3300000>;
 113 +               regulator-boot-on;
 114 +               regulator-always-on;
 115 +       };
 116 +
 117 +       reg_5v: regulator-5v {
 118 +               compatible = "regulator-fixed";
 119 +               regulator-name = "fixed-5V";
 120 +               regulator-min-microvolt = <5000000>;
 121 +               regulator-max-microvolt = <5000000>;
 122 +               regulator-boot-on;
 123 +               regulator-always-on;
 124 +       };
 125 +
 126 +       gpio-keys {
 127 +               compatible = "gpio-keys";
 128 +               pinctrl-names = "default";
 129 +               pinctrl-0 = <&key_pins_a>;
 130 +
 131 +               factory {
 132 +                       label = "factory";
 133 +                       linux,code = <KEY_RESTART>;
 134 +                       gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 135 +               };
 136 +       };
 137 +
 138 +       leds {
 139 +               compatible = "gpio-leds";
 140 +               pinctrl-names = "default";
 141 +               pinctrl-0 = <&led_pins_unielec>;
 142 +
 143 +               led3 {
 144 +                       label = "u7623-01:green:led3";
 145 +                       gpios = <&pio 14 GPIO_ACTIVE_LOW>;
 146 +                       default-state = "off";
 147 +               };
 148 +
 149 +               led4 {
 150 +                       label = "u7623-01:green:led4";
 151 +                       gpios = <&pio 15 GPIO_ACTIVE_LOW>;
 152 +                       default-state = "off";
 153 +               };
 154 +       };
 155 +
 156 +       memory@80000000 {
 157 +               device_type = "memory";
 158 +               reg = <0 0x80000000 0 0x40000000>;
 159 +       };
 160 +
 161 +       mt7530: switch@0 {
 162 +               compatible = "mediatek,mt7530";
 163 +               #address-cells = <1>;
 164 +               #size-cells = <0>;
 165 +       };
 166 +};
 167 +
 168 +&crypto {
 169 +       status = "okay";
 170 +};
 171 +
 172 +&eth {
 173 +       status = "okay";
 174 +
 175 +       gmac0: mac@0 {
 176 +               compatible = "mediatek,eth-mac";
 177 +               reg = <0>;
 178 +               phy-mode = "trgmii";
 179 +
 180 +               fixed-link {
 181 +                       speed = <1000>;
 182 +                       full-duplex;
 183 +                       pause;
 184 +               };
 185 +       };
 186 +
 187 +       mdio: mdio-bus {
 188 +               #address-cells = <1>;
 189 +               #size-cells = <0>;
 190 +               phy5: ethernet-phy@5 {
 191 +                       reg = <5>;
 192 +                       phy-mode = "rgmii-rxid";
 193 +               };
 194 +       };
 195 +};
 196 +
 197 +&mt7530 {
 198 +       compatible = "mediatek,mt7530";
 199 +       #address-cells = <1>;
 200 +       #size-cells = <0>;
 201 +       reg = <0>;
 202 +       pinctrl-names = "default";
 203 +       mediatek,mcm;
 204 +       resets = <&ethsys 2>;
 205 +       reset-names = "mcm";
 206 +       core-supply = <&mt6323_vpa_reg>;
 207 +       io-supply = <&mt6323_vemc3v3_reg>;
 208 +
 209 +       dsa,mii-bus = <&mdio>;
 210 +
 211 +       ports {
 212 +               #address-cells = <1>;
 213 +               #size-cells = <0>;
 214 +               reg = <0>;
 215 +
 216 +               port@0 {
 217 +                       reg = <0>;
 218 +                       label = "lan0";
 219 +                       cpu = <&cpu_port0>;
 220 +               };
 221 +
 222 +               port@1 {
 223 +                       reg = <1>;
 224 +                       label = "lan1";
 225 +                       cpu = <&cpu_port0>;
 226 +               };
 227 +
 228 +               port@2 {
 229 +                       reg = <2>;
 230 +                       label = "lan2";
 231 +                       cpu = <&cpu_port0>;
 232 +               };
 233 +
 234 +               port@3 {
 235 +                       reg = <3>;
 236 +                       label = "lan3";
 237 +                       cpu = <&cpu_port0>;
 238 +               };
 239 +
 240 +               port@4 {
 241 +                       reg = <4>;
 242 +                       label = "wan";
 243 +                       cpu = <&cpu_port0>;
 244 +               };
 245 +
 246 +               cpu_port0: port@6 {
 247 +                       reg = <6>;
 248 +                       label = "cpu";
 249 +                       ethernet = <&gmac0>;
 250 +                       phy-mode = "trgmii";
 251 +
 252 +                       fixed-link {
 253 +                               speed = <1000>;
 254 +                               full-duplex;
 255 +                       };
 256 +               };
 257 +       };
 258 +};
 259 +
 260 +&mmc0 {
 261 +       pinctrl-names = "default", "state_uhs";
 262 +       pinctrl-0 = <&mmc0_pins_default>;
 263 +       pinctrl-1 = <&mmc0_pins_uhs>;
 264 +       status = "okay";
 265 +       bus-width = <8>;
 266 +       max-frequency = <50000000>;
 267 +       cap-mmc-highspeed;
 268 +       vmmc-supply = <&reg_3p3v>;
 269 +       vqmmc-supply = <&reg_1p8v>;
 270 +       non-removable;
 271 +};
 272 +
 273 +&pio {
 274 +       key_pins_a: keys-alt {
 275 +               pins-keys {
 276 +                       pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
 277 +                                <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
 278 +                       input-enable;
 279 +               };
 280 +       };
 281 +
 282 +       led_pins_unielec: leds-unielec {
 283 +               pins-leds {
 284 +                       pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
 285 +                                <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
 286 +               };
 287 +       };
 288 +
 289 +       mmc0_pins_default: mmc0default {
 290 +               pins_cmd_dat {
 291 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 292 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 293 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 294 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 295 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 296 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 297 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 298 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 299 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 300 +                       input-enable;
 301 +                       bias-pull-up;
 302 +               };
 303 +
 304 +               pins_clk {
 305 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 306 +                       bias-pull-down;
 307 +               };
 308 +
 309 +               pins_rst {
 310 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 311 +                       bias-pull-up;
 312 +               };
 313 +       };
 314 +
 315 +       mmc0_pins_uhs: mmc0 {
 316 +               pins_cmd_dat {
 317 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 318 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 319 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 320 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 321 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 322 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 323 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 324 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 325 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 326 +                       input-enable;
 327 +                       drive-strength = <MTK_DRIVE_2mA>;
 328 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 329 +               };
 330 +
 331 +               pins_clk {
 332 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 333 +                       drive-strength = <MTK_DRIVE_2mA>;
 334 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 335 +               };
 336 +
 337 +               pins_rst {
 338 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 339 +                       bias-pull-up;
 340 +               };
 341 +       };
 342 +
 343 +       pwm_pins_a: pwm@0 {
 344 +               pins_pwm {
 345 +                       pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
 346 +                                <MT7623_PIN_204_PWM1_FUNC_PWM1>,
 347 +                                <MT7623_PIN_205_PWM2_FUNC_PWM2>,
 348 +                                <MT7623_PIN_206_PWM3_FUNC_PWM3>,
 349 +                                <MT7623_PIN_207_PWM4_FUNC_PWM4>;
 350 +               };
 351 +       };
 352 +
 353 +       uart2_pins_b: uart@2 {
 354 +               pins_dat {
 355 +                       pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
 356 +                                <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
 357 +               };
 358 +       };
 359 +
 360 +       pcie_default: pcie_pin_default {
 361 +               pins_cmd_dat {
 362 +                       pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
 363 +                                <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
 364 +                       bias-disable;
 365 +               };
 366 +       };
 367 +};
 368 +
 369 +&pwm {
 370 +       pinctrl-names = "default";
 371 +       pinctrl-0 = <&pwm_pins_a>;
 372 +       status = "okay";
 373 +};
 374 +
 375 +&pwrap {
 376 +       mt6323 {
 377 +               mt6323led: led {
 378 +                       compatible = "mediatek,mt6323-led";
 379 +                       #address-cells = <1>;
 380 +                       #size-cells = <0>;
 381 +
 382 +                       led@0 {
 383 +                               reg = <0>;
 384 +                               label = "led0";
 385 +                               default-state = "off";
 386 +                       };
 387 +               };
 388 +       };
 389 +};
 390 +
 391 +&uart2 {
 392 +       pinctrl-names = "default";
 393 +       pinctrl-0 = <&uart2_pins_b>;
 394 +       status = "okay";
 395 +};
 396 +
 397 +&usb1 {
 398 +       vusb33-supply = <&reg_3p3v>;
 399 +       vbus-supply = <&reg_3p3v>;
 400 +       status = "okay";
 401 +};
 402 +
 403 +&u3phy1 {
 404 +       status = "okay";
 405 +};
 406 +
 407 +&u3phy2 {
 408 +       status = "okay";
 409 +       mediatek,phy-switch = <&hifsys>;
 410 +};
 411 +
 412 +&pcie {
 413 +       pinctrl-names = "default";
 414 +       pinctrl-0 = <&pcie_default>;
 415 +       status = "okay";
 416 +
 417 +       pcie@1,0 {
 418 +               status = "okay";
 419 +       };
 420 +
 421 +       pcie@2,0 {
 422 +               status = "okay";
 423 +       };
 424 +};
 425 +
 426 +&pcie1_phy {
 427 +       status = "okay";
 428 +};
 429 +
 430 --
 431 2.14.1
 432