target/linux/mediatek/patches-4.14/0219-arm64-dts-mt7622-add-PCIe-device-nodes.patch

   1 From e84732bd6022dd12839dd34d508eb27428367c24 Mon Sep 17 00:00:00 2001
   2 From: Ryder Lee <ryder.lee@mediatek.com>
   3 Date: Wed, 20 Dec 2017 15:57:30 +0800
   4 Subject: [PATCH 219/224] arm64: dts: mt7622: add PCIe device nodes
   5
   6 This patch adds PCIe support fot MT7622.
   7
   8 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 ---
  11  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 10 ++++
  12  arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 74 ++++++++++++++++++++++++++++
  13  2 files changed, 84 insertions(+)
  14
  15 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  16 index e2bd93e1b49b..72ef4434bcef 100644
  17 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  18 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  19 @@ -54,6 +54,16 @@
  20         };
  21  };
  22
  23 +&pcie {
  24 +       pinctrl-names = "default";
  25 +       pinctrl-0 = <&pcie0_pins>;
  26 +       status = "okay";
  27 +
  28 +       pcie@0,0 {
  29 +               status = "okay";
  30 +       };
  31 +};
  32 +
  33  &pio {
  34         /* eMMC is shared pin with parallel NAND */
  35         emmc_pins_default: emmc-pins-default {
  36 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  37 index 95f947eb824c..cc026ebda2f4 100644
  38 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  39 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  40 @@ -542,6 +542,80 @@
  41                 #reset-cells = <1>;
  42         };
  43
  44 +       pcie: pcie@1a140000 {
  45 +               compatible = "mediatek,mt7622-pcie";
  46 +               device_type = "pci";
  47 +               reg = <0 0x1a140000 0 0x1000>,
  48 +                     <0 0x1a143000 0 0x1000>,
  49 +                     <0 0x1a145000 0 0x1000>;
  50 +               reg-names = "subsys", "port0", "port1";
  51 +               #address-cells = <3>;
  52 +               #size-cells = <2>;
  53 +               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
  54 +                            <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
  55 +               clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
  56 +                        <&pciesys CLK_PCIE_P1_MAC_EN>,
  57 +                        <&pciesys CLK_PCIE_P0_AHB_EN>,
  58 +                        <&pciesys CLK_PCIE_P0_AHB_EN>,
  59 +                        <&pciesys CLK_PCIE_P0_AUX_EN>,
  60 +                        <&pciesys CLK_PCIE_P1_AUX_EN>,
  61 +                        <&pciesys CLK_PCIE_P0_AXI_EN>,
  62 +                        <&pciesys CLK_PCIE_P1_AXI_EN>,
  63 +                        <&pciesys CLK_PCIE_P0_OBFF_EN>,
  64 +                        <&pciesys CLK_PCIE_P1_OBFF_EN>,
  65 +                        <&pciesys CLK_PCIE_P0_PIPE_EN>,
  66 +                        <&pciesys CLK_PCIE_P1_PIPE_EN>;
  67 +               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
  68 +                             "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
  69 +                             "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
  70 +               power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
  71 +               bus-range = <0x00 0xff>;
  72 +               ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
  73 +               status = "disabled";
  74 +
  75 +               pcie0: pcie@0,0 {
  76 +                       reg = <0x0000 0 0 0 0>;
  77 +                       #address-cells = <3>;
  78 +                       #size-cells = <2>;
  79 +                       #interrupt-cells = <1>;
  80 +                       ranges;
  81 +                       status = "disabled";
  82 +
  83 +                       num-lanes = <1>;
  84 +                       interrupt-map-mask = <0 0 0 7>;
  85 +                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
  86 +                                       <0 0 0 2 &pcie_intc0 1>,
  87 +                                       <0 0 0 3 &pcie_intc0 2>,
  88 +                                       <0 0 0 4 &pcie_intc0 3>;
  89 +                       pcie_intc0: interrupt-controller {
  90 +                               interrupt-controller;
  91 +                               #address-cells = <0>;
  92 +                               #interrupt-cells = <1>;
  93 +                       };
  94 +               };
  95 +
  96 +               pcie1: pcie@1,0 {
  97 +                       reg = <0x0800 0 0 0 0>;
  98 +                       #address-cells = <3>;
  99 +                       #size-cells = <2>;
 100 +                       #interrupt-cells = <1>;
 101 +                       ranges;
 102 +                       status = "disabled";
 103 +
 104 +                       num-lanes = <1>;
 105 +                       interrupt-map-mask = <0 0 0 7>;
 106 +                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 107 +                                       <0 0 0 2 &pcie_intc1 1>,
 108 +                                       <0 0 0 3 &pcie_intc1 2>,
 109 +                                       <0 0 0 4 &pcie_intc1 3>;
 110 +                       pcie_intc1: interrupt-controller {
 111 +                               interrupt-controller;
 112 +                               #address-cells = <0>;
 113 +                               #interrupt-cells = <1>;
 114 +                       };
 115 +               };
 116 +       };
 117 +
 118         ethsys: syscon@1b000000 {
 119                 compatible = "mediatek,mt7622-ethsys",
 120                              "syscon";
 121 --
 122 2.11.0
 123