d92c0c50fbdb50119713866a5e6ba37c21cc8a4b
[openwrt/staging/lynxis.git] / target / linux / mediatek / patches-4.14 / 0206-dt-bindings-clock-mediatek-update-audsys-documentati.patch
1 From e6d9c3121f2a8b92bd6202d6a32e7d428990d7d7 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Tue, 6 Mar 2018 17:09:29 +0800
4 Subject: [PATCH 206/224] dt-bindings: clock: mediatek: update audsys
5 documentation to adapt MFD device
6
7 The MediaTek audio hardware block that exposes functionalities that are
8 handled by separate subsystems in the kernel. These functions are all
9 mapped somewhere at 0x112xxxxx, and there are some control bits are mixed
10 up with other functions within the same registers.
11
12 This patch modifies example to illustrate child nodes.
13
14 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
15 ---
16 .../bindings/arm/mediatek/mediatek,audsys.txt | 19 ++++++++++++++-----
17 1 file changed, 14 insertions(+), 5 deletions(-)
18
19 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
20 index 9b8f578d5e19..97b304eaa47c 100644
21 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
22 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
23 @@ -13,10 +13,19 @@ The AUDSYS controller uses the common clk binding from
24 Documentation/devicetree/bindings/clock/clock-bindings.txt
25 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
26
27 +Required sub-nodes:
28 +-------
29 +For common binding part and usage, refer to
30 +../sonud/mt2701-afe-pcm.txt.
31 +
32 Example:
33
34 -audsys: audsys@11220000 {
35 - compatible = "mediatek,mt7622-audsys", "syscon";
36 - reg = <0 0x11220000 0 0x1000>;
37 - #clock-cells = <1>;
38 -};
39 + audsys: clock-controller@11220000 {
40 + compatible = "mediatek,mt7622-audsys", "syscon";
41 + reg = <0 0x11220000 0 0x2000>;
42 + #clock-cells = <1>;
43 +
44 + afe: audio-controller {
45 + ...
46 + };
47 + };
48 --
49 2.11.0
50