target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch

   1 From 9257240bcaf8f9ee6878357e00e7ab511ad6d325 Mon Sep 17 00:00:00 2001
   2 From: Chaotian Jing <chaotian.jing@mediatek.com>
   3 Date: Mon, 16 Oct 2017 09:46:35 +0800
   4 Subject: [PATCH 156/224] mmc: mediatek: add stop_clk fix and enhance_rx
   5  support
   6
   7 mt2712 supports stop_clk fix and enhance_rx, which can improve
   8 host stability.
   9
  10 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
  11 Tested-by: Sean Wang <sean.wang@mediatek.com>
  12 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  13 ---
  14  drivers/mmc/host/mtk-sd.c | 47 +++++++++++++++++++++++++++++++++++++++++++----
  15  1 file changed, 43 insertions(+), 4 deletions(-)
  16
  17 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
  18 index eceaee86ba4d..94d16a3a8d94 100644
  19 --- a/drivers/mmc/host/mtk-sd.c
  20 +++ b/drivers/mmc/host/mtk-sd.c
  21 @@ -67,6 +67,7 @@
  22  #define SDC_RESP2        0x48
  23  #define SDC_RESP3        0x4c
  24  #define SDC_BLK_NUM      0x50
  25 +#define SDC_ADV_CFG0     0x64
  26  #define EMMC_IOCON       0x7c
  27  #define SDC_ACMD_RESP    0x80
  28  #define MSDC_DMA_SA      0x90
  29 @@ -80,6 +81,7 @@
  30  #define PAD_DS_TUNE      0x188
  31  #define PAD_CMD_TUNE     0x18c
  32  #define EMMC50_CFG0      0x208
  33 +#define SDC_FIFO_CFG     0x228
  34
  35  /*--------------------------------------------------------------------------*/
  36  /* Register Mask                                                            */
  37 @@ -188,6 +190,9 @@
  38  #define SDC_STS_CMDBUSY         (0x1 << 1)     /* RW */
  39  #define SDC_STS_SWR_COMPL       (0x1 << 31)    /* RW */
  40
  41 +/* SDC_ADV_CFG0 mask */
  42 +#define SDC_RX_ENHANCE_EN      (0x1 << 20)     /* RW */
  43 +
  44  /* MSDC_DMA_CTRL mask */
  45  #define MSDC_DMA_CTRL_START     (0x1 << 0)     /* W */
  46  #define MSDC_DMA_CTRL_STOP      (0x1 << 1)     /* W */
  47 @@ -217,6 +222,8 @@
  48  #define MSDC_PATCH_BIT_SPCPUSH    (0x1 << 29)  /* RW */
  49  #define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)  /* RW */
  50
  51 +#define MSDC_PATCH_BIT1_STOP_DLY  (0xf << 8)    /* RW */
  52 +
  53  #define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
  54  #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
  55  #define MSDC_PB2_RESPWAIT         (0x3 << 2)    /* RW */
  56 @@ -242,6 +249,9 @@
  57  #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
  58  #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
  59
  60 +#define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
  61 +#define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
  62 +
  63  #define REQ_CMD_EIO  (0x1 << 0)
  64  #define REQ_CMD_TMO  (0x1 << 1)
  65  #define REQ_DAT_ERR  (0x1 << 2)
  66 @@ -308,6 +318,7 @@ struct msdc_save_para {
  67         u32 pad_ds_tune;
  68         u32 pad_cmd_tune;
  69         u32 emmc50_cfg0;
  70 +       u32 sdc_fifo_cfg;
  71  };
  72
  73  struct mtk_mmc_compatible {
  74 @@ -317,6 +328,8 @@ struct mtk_mmc_compatible {
  75         bool async_fifo;
  76         bool data_tune;
  77         bool busy_check;
  78 +       bool stop_clk_fix;
  79 +       bool enhance_rx;
  80  };
  81
  82  struct msdc_tune_para {
  83 @@ -382,6 +395,8 @@ static const struct mtk_mmc_compatible mt8135_compat = {
  84         .async_fifo = false,
  85         .data_tune = false,
  86         .busy_check = false,
  87 +       .stop_clk_fix = false,
  88 +       .enhance_rx = false,
  89  };
  90
  91  static const struct mtk_mmc_compatible mt8173_compat = {
  92 @@ -391,6 +406,8 @@ static const struct mtk_mmc_compatible mt8173_compat = {
  93         .async_fifo = false,
  94         .data_tune = false,
  95         .busy_check = false,
  96 +       .stop_clk_fix = false,
  97 +       .enhance_rx = false,
  98  };
  99
 100  static const struct mtk_mmc_compatible mt2701_compat = {
 101 @@ -400,6 +417,8 @@ static const struct mtk_mmc_compatible mt2701_compat = {
 102         .async_fifo = true,
 103         .data_tune = true,
 104         .busy_check = false,
 105 +       .stop_clk_fix = false,
 106 +       .enhance_rx = false,
 107  };
 108
 109  static const struct mtk_mmc_compatible mt2712_compat = {
 110 @@ -409,6 +428,8 @@ static const struct mtk_mmc_compatible mt2712_compat = {
 111         .async_fifo = true,
 112         .data_tune = true,
 113         .busy_check = true,
 114 +       .stop_clk_fix = true,
 115 +       .enhance_rx = true,
 116  };
 117
 118  static const struct of_device_id msdc_of_ids[] = {
 119 @@ -1280,15 +1301,31 @@ static void msdc_init_hw(struct msdc_host *host)
 120         sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
 121         writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
 122         sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
 123 +
 124 +       if (host->dev_comp->stop_clk_fix) {
 125 +               sdr_set_field(host->base + MSDC_PATCH_BIT1,
 126 +                             MSDC_PATCH_BIT1_STOP_DLY, 3);
 127 +               sdr_clr_bits(host->base + SDC_FIFO_CFG,
 128 +                            SDC_FIFO_CFG_WRVALIDSEL);
 129 +               sdr_clr_bits(host->base + SDC_FIFO_CFG,
 130 +                            SDC_FIFO_CFG_RDVALIDSEL);
 131 +       }
 132 +
 133         if (host->dev_comp->busy_check)
 134                 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
 135 +
 136         if (host->dev_comp->async_fifo) {
 137                 sdr_set_field(host->base + MSDC_PATCH_BIT2,
 138                               MSDC_PB2_RESPWAIT, 3);
 139 -               sdr_set_field(host->base + MSDC_PATCH_BIT2,
 140 -                             MSDC_PB2_RESPSTSENSEL, 2);
 141 -               sdr_set_field(host->base + MSDC_PATCH_BIT2,
 142 -                             MSDC_PB2_CRCSTSENSEL, 2);
 143 +               if (host->dev_comp->enhance_rx) {
 144 +                       sdr_set_bits(host->base + SDC_ADV_CFG0,
 145 +                                    SDC_RX_ENHANCE_EN);
 146 +               } else {
 147 +                       sdr_set_field(host->base + MSDC_PATCH_BIT2,
 148 +                                     MSDC_PB2_RESPSTSENSEL, 2);
 149 +                       sdr_set_field(host->base + MSDC_PATCH_BIT2,
 150 +                                     MSDC_PB2_CRCSTSENSEL, 2);
 151 +               }
 152                 /* use async fifo, then no need tune internal delay */
 153                 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
 154                              MSDC_PATCH_BIT2_CFGRESP);
 155 @@ -1933,6 +1970,7 @@ static void msdc_save_reg(struct msdc_host *host)
 156         host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
 157         host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
 158         host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
 159 +       host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
 160  }
 161
 162  static void msdc_restore_reg(struct msdc_host *host)
 163 @@ -1949,6 +1987,7 @@ static void msdc_restore_reg(struct msdc_host *host)
 164         writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
 165         writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
 166         writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
 167 +       writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
 168  }
 169
 170  static int msdc_runtime_suspend(struct device *dev)
 171 --
 172 2.11.0
 173