target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch

   1 From acfa4eba7a4391d443b33a3d90a07eae0ef2ebca Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 5 Oct 2017 11:50:22 +0800
   4 Subject: [PATCH 147/224] dt-bindings: clock: mediatek: document clk bindings
   5  for MediaTek MT7622 SoC
   6
   7 This patch adds the binding documentation for apmixedsys, ethsys, hifsys,
   8 infracfg, pericfg, topckgen and audsys for MT7622.
   9
  10 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
  11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  12 Acked-by: Rob Herring <robh@kernel.org>
  13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  14 ---
  15  .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
  16  .../bindings/arm/mediatek/mediatek,audsys.txt      | 22 ++++++++++++++++++++++
  17  .../bindings/arm/mediatek/mediatek,ethsys.txt      |  1 +
  18  .../bindings/arm/mediatek/mediatek,hifsys.txt      |  1 +
  19  .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
  20  .../bindings/arm/mediatek/mediatek,pciesys.txt     | 22 ++++++++++++++++++++++
  21  .../bindings/arm/mediatek/mediatek,pericfg.txt     |  1 +
  22  .../bindings/arm/mediatek/mediatek,sgmiisys.txt    | 22 ++++++++++++++++++++++
  23  .../bindings/arm/mediatek/mediatek,ssusbsys.txt    | 22 ++++++++++++++++++++++
  24  .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
  25  10 files changed, 94 insertions(+)
  26  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
  27  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
  28  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
  29  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
  30
  31 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
  32 index 19fc116346d6..b404d592ce58 100644
  33 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
  34 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
  35 @@ -9,6 +9,7 @@ Required Properties:
  36         - "mediatek,mt2701-apmixedsys"
  37         - "mediatek,mt2712-apmixedsys", "syscon"
  38         - "mediatek,mt6797-apmixedsys"
  39 +       - "mediatek,mt7622-apmixedsys"
  40         - "mediatek,mt8135-apmixedsys"
  41         - "mediatek,mt8173-apmixedsys"
  42  - #clock-cells: Must be 1
  43 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
  44 new file mode 100644
  45 index 000000000000..9b8f578d5e19
  46 --- /dev/null
  47 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
  48 @@ -0,0 +1,22 @@
  49 +MediaTek AUDSYS controller
  50 +============================
  51 +
  52 +The MediaTek AUDSYS controller provides various clocks to the system.
  53 +
  54 +Required Properties:
  55 +
  56 +- compatible: Should be one of:
  57 +       - "mediatek,mt7622-audsys", "syscon"
  58 +- #clock-cells: Must be 1
  59 +
  60 +The AUDSYS controller uses the common clk binding from
  61 +Documentation/devicetree/bindings/clock/clock-bindings.txt
  62 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  63 +
  64 +Example:
  65 +
  66 +audsys: audsys@11220000 {
  67 +       compatible = "mediatek,mt7622-audsys", "syscon";
  68 +       reg = <0 0x11220000 0 0x1000>;
  69 +       #clock-cells = <1>;
  70 +};
  71 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  72 index 768f3a5bc055..7aa3fa167668 100644
  73 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  74 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  75 @@ -7,6 +7,7 @@ Required Properties:
  76
  77  - compatible: Should be:
  78         - "mediatek,mt2701-ethsys", "syscon"
  79 +       - "mediatek,mt7622-ethsys", "syscon"
  80  - #clock-cells: Must be 1
  81
  82  The ethsys controller uses the common clk binding from
  83 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
  84 index beed7b594cea..f5629d64cef2 100644
  85 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
  86 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
  87 @@ -8,6 +8,7 @@ Required Properties:
  88
  89  - compatible: Should be:
  90         - "mediatek,mt2701-hifsys", "syscon"
  91 +       - "mediatek,mt7622-hifsys", "syscon"
  92  - #clock-cells: Must be 1
  93
  94  The hifsys controller uses the common clk binding from
  95 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
  96 index a3430cd96d0f..566f153f9f83 100644
  97 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
  98 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
  99 @@ -10,6 +10,7 @@ Required Properties:
 100         - "mediatek,mt2701-infracfg", "syscon"
 101         - "mediatek,mt2712-infracfg", "syscon"
 102         - "mediatek,mt6797-infracfg", "syscon"
 103 +       - "mediatek,mt7622-infracfg", "syscon"
 104         - "mediatek,mt8135-infracfg", "syscon"
 105         - "mediatek,mt8173-infracfg", "syscon"
 106  - #clock-cells: Must be 1
 107 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
 108 new file mode 100644
 109 index 000000000000..d5d5f1227665
 110 --- /dev/null
 111 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
 112 @@ -0,0 +1,22 @@
 113 +MediaTek PCIESYS controller
 114 +============================
 115 +
 116 +The MediaTek PCIESYS controller provides various clocks to the system.
 117 +
 118 +Required Properties:
 119 +
 120 +- compatible: Should be:
 121 +       - "mediatek,mt7622-pciesys", "syscon"
 122 +- #clock-cells: Must be 1
 123 +
 124 +The PCIESYS controller uses the common clk binding from
 125 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 126 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 127 +
 128 +Example:
 129 +
 130 +pciesys: pciesys@1a100800 {
 131 +       compatible = "mediatek,mt7622-pciesys", "syscon";
 132 +       reg = <0 0x1a100800 0 0x1000>;
 133 +       #clock-cells = <1>;
 134 +};
 135 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 136 index d9f092eb3550..fb58ca8c2770 100644
 137 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 138 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 139 @@ -9,6 +9,7 @@ Required Properties:
 140  - compatible: Should be one of:
 141         - "mediatek,mt2701-pericfg", "syscon"
 142         - "mediatek,mt2712-pericfg", "syscon"
 143 +       - "mediatek,mt7622-pericfg", "syscon"
 144         - "mediatek,mt8135-pericfg", "syscon"
 145         - "mediatek,mt8173-pericfg", "syscon"
 146  - #clock-cells: Must be 1
 147 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
 148 new file mode 100644
 149 index 000000000000..d113b8e741f3
 150 --- /dev/null
 151 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
 152 @@ -0,0 +1,22 @@
 153 +MediaTek SGMIISYS controller
 154 +============================
 155 +
 156 +The MediaTek SGMIISYS controller provides various clocks to the system.
 157 +
 158 +Required Properties:
 159 +
 160 +- compatible: Should be:
 161 +       - "mediatek,mt7622-sgmiisys", "syscon"
 162 +- #clock-cells: Must be 1
 163 +
 164 +The SGMIISYS controller uses the common clk binding from
 165 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 166 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 167 +
 168 +Example:
 169 +
 170 +sgmiisys: sgmiisys@1b128000 {
 171 +       compatible = "mediatek,mt7622-sgmiisys", "syscon";
 172 +       reg = <0 0x1b128000 0 0x1000>;
 173 +       #clock-cells = <1>;
 174 +};
 175 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
 176 new file mode 100644
 177 index 000000000000..00760019da00
 178 --- /dev/null
 179 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
 180 @@ -0,0 +1,22 @@
 181 +MediaTek SSUSBSYS controller
 182 +============================
 183 +
 184 +The MediaTek SSUSBSYS controller provides various clocks to the system.
 185 +
 186 +Required Properties:
 187 +
 188 +- compatible: Should be:
 189 +       - "mediatek,mt7622-ssusbsys", "syscon"
 190 +- #clock-cells: Must be 1
 191 +
 192 +The SSUSBSYS controller uses the common clk binding from
 193 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 194 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 195 +
 196 +Example:
 197 +
 198 +ssusbsys: ssusbsys@1a000000 {
 199 +       compatible = "mediatek,mt7622-ssusbsys", "syscon";
 200 +       reg = <0 0x1a000000 0 0x1000>;
 201 +       #clock-cells = <1>;
 202 +};
 203 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 204 index 2024fc909d69..24014a7e2332 100644
 205 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 206 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 207 @@ -9,6 +9,7 @@ Required Properties:
 208         - "mediatek,mt2701-topckgen"
 209         - "mediatek,mt2712-topckgen", "syscon"
 210         - "mediatek,mt6797-topckgen"
 211 +       - "mediatek,mt7622-topckgen"
 212         - "mediatek,mt8135-topckgen"
 213         - "mediatek,mt8173-topckgen"
 214  - #clock-cells: Must be 1
 215 --
 216 2.11.0
 217