projects / openwrt / staging / stintel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
mediatek: dts: mt7988a: remove boottrap hack
[openwrt/staging/stintel.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/reset/ti-syscon.h>
11 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "mediatek,mt7988";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 clk40m: oscillator@0 {
22 compatible = "fixed-clock";
23 clock-frequency = <40000000>;
24 #clock-cells = <0>;
25 clock-output-names = "clkxtal";
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31 cpu0: cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a73";
34 enable-method = "psci";
35 reg = <0x0>;
36 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
37 <&topckgen CLK_TOP_XTAL>;
38 clock-names = "cpu", "intermediate";
39 operating-points-v2 = <&cluster0_opp>;
40 mediatek,cci = <&cci>;
41 };
42
43 cpu1: cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a73";
46 enable-method = "psci";
47 reg = <0x1>;
48 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
49 <&topckgen CLK_TOP_XTAL>;
50 clock-names = "cpu", "intermediate";
51 operating-points-v2 = <&cluster0_opp>;
52 mediatek,cci = <&cci>;
53 };
54
55 cpu2: cpu@2 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a73";
58 enable-method = "psci";
59 reg = <0x2>;
60 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
61 <&topckgen CLK_TOP_XTAL>;
62 clock-names = "cpu", "intermediate";
63 operating-points-v2 = <&cluster0_opp>;
64 mediatek,cci = <&cci>;
65 };
66
67 cpu3: cpu@3 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a73";
70 enable-method = "psci";
71 reg = <0x3>;
72 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
73 <&topckgen CLK_TOP_XTAL>;
74 clock-names = "cpu", "intermediate";
75 operating-points-v2 = <&cluster0_opp>;
76 mediatek,cci = <&cci>;
77 };
78
79 cluster0_opp: opp_table0 {
80 compatible = "operating-points-v2";
81 opp-shared;
82 opp00 {
83 opp-hz = /bits/ 64 <800000000>;
84 opp-microvolt = <850000>;
85 };
86 opp01 {
87 opp-hz = /bits/ 64 <1100000000>;
88 opp-microvolt = <850000>;
89 };
90 opp02 {
91 opp-hz = /bits/ 64 <1500000000>;
92 opp-microvolt = <850000>;
93 };
94 opp03 {
95 opp-hz = /bits/ 64 <1800000000>;
96 opp-microvolt = <900000>;
97 };
98 };
99 };
100
101 cci: cci {
102 compatible = "mediatek,mt7988-cci",
103 "mediatek,mt8183-cci";
104 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
105 <&topckgen CLK_TOP_XTAL>;
106 clock-names = "cci", "intermediate";
107 operating-points-v2 = <&cci_opp>;
108 };
109
110 cci_opp: opp_table_cci {
111 compatible = "operating-points-v2";
112 opp-shared;
113 opp00 {
114 opp-hz = /bits/ 64 <480000000>;
115 opp-microvolt = <850000>;
116 };
117 opp01 {
118 opp-hz = /bits/ 64 <660000000>;
119 opp-microvolt = <850000>;
120 };
121 opp02 {
122 opp-hz = /bits/ 64 <900000000>;
123 opp-microvolt = <850000>;
124 };
125 opp03 {
126 opp-hz = /bits/ 64 <1080000000>;
127 opp-microvolt = <900000>;
128 };
129 };
130
131 pmu {
132 compatible = "arm,cortex-a73-pmu";
133 interrupt-parent = <&gic>;
134 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
135 };
136
137 psci {
138 compatible = "arm,psci-0.2";
139 method = "smc";
140 };
141
142 reserved-memory {
143 #address-cells = <2>;
144 #size-cells = <2>;
145 ranges;
146
147 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
148 secmon_reserved: secmon@43000000 {
149 reg = <0 0x43000000 0 0x30000>;
150 no-map;
151 };
152 };
153
154 timer {
155 compatible = "arm,armv8-timer";
156 interrupt-parent = <&gic>;
157 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
158 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
159 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
160 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
161 };
162
163 soc {
164 #address-cells = <2>;
165 #size-cells = <2>;
166 compatible = "simple-bus";
167 ranges;
168
169 gic: interrupt-controller@c000000 {
170 compatible = "arm,gic-v3";
171 #interrupt-cells = <3>;
172 interrupt-parent = <&gic>;
173 interrupt-controller;
174 reg = <0 0x0c000000 0 0x40000>, /* GICD */
175 <0 0x0c080000 0 0x200000>, /* GICR */
176 <0 0x0c400000 0 0x2000>, /* GICC */
177 <0 0x0c410000 0 0x1000>, /* GICH */
178 <0 0x0c420000 0 0x2000>; /* GICV */
179
180 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
181 };
182
183 phyfw: phy-firmware@f000000 {
184 compatible = "mediatek,2p5gphy-fw";
185 reg = <0 0x0f000000 0 0x8000>,
186 <0 0x0f100000 0 0x20000>,
187 <0 0x0f0f0000 0 0x200>;
188 };
189
190 infracfg: infracfg@10001000 {
191 compatible = "mediatek,mt7988-infracfg", "syscon";
192 reg = <0 0x10001000 0 0x1000>;
193 #clock-cells = <1>;
194 };
195
196 topckgen: topckgen@1001b000 {
197 compatible = "mediatek,mt7988-topckgen", "syscon";
198 reg = <0 0x1001b000 0 0x1000>;
199 #clock-cells = <1>;
200 };
201
202 watchdog: watchdog@1001c000 {
203 compatible = "mediatek,mt7988-wdt",
204 "mediatek,mt6589-wdt",
205 "syscon";
206 reg = <0 0x1001c000 0 0x1000>;
207 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
208 #reset-cells = <1>;
209 };
210
211 apmixedsys: apmixedsys@1001e000 {
212 compatible = "mediatek,mt7988-apmixedsys";
213 reg = <0 0x1001e000 0 0x1000>;
214 #clock-cells = <1>;
215 };
216
217 pio: pinctrl@1001f000 {
218 compatible = "mediatek,mt7988-pinctrl", "syscon";
219 reg = <0 0x1001f000 0 0x1000>,
220 <0 0x11c10000 0 0x1000>,
221 <0 0x11d00000 0 0x1000>,
222 <0 0x11d20000 0 0x1000>,
223 <0 0x11e00000 0 0x1000>,
224 <0 0x11f00000 0 0x1000>,
225 <0 0x1000b000 0 0x1000>;
226 reg-names = "gpio_base", "iocfg_tr_base",
227 "iocfg_br_base", "iocfg_rb_base",
228 "iocfg_lb_base", "iocfg_tl_base", "eint";
229 gpio-controller;
230 #gpio-cells = <2>;
231 gpio-ranges = <&pio 0 0 83>;
232 interrupt-controller;
233 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
234 interrupt-parent = <&gic>;
235 #interrupt-cells = <2>;
236
237 mdio0_pins: mdio0-pins {
238 mux {
239 function = "eth";
240 groups = "mdc_mdio0";
241 };
242
243 conf {
244 groups = "mdc_mdio0";
245 drive-strength = <MTK_DRIVE_8mA>;
246 };
247 };
248
249 i2c0_pins: i2c0-pins-g0 {
250 mux {
251 function = "i2c";
252 groups = "i2c0_1";
253 };
254 };
255
256 i2c1_pins: i2c1-pins-g0 {
257 mux {
258 function = "i2c";
259 groups = "i2c1_0";
260 };
261 };
262
263 i2c2_pins: i2c2-pins-g0 {
264 mux {
265 function = "i2c";
266 groups = "i2c2_1";
267 };
268 };
269
270 gbe0_led0_pins: gbe0-pins {
271 mux {
272 function = "led";
273 groups = "gbe0_led0";
274 };
275 };
276
277 gbe1_led0_pins: gbe1-pins {
278 mux {
279 function = "led";
280 groups = "gbe1_led0";
281 };
282 };
283
284 gbe2_led0_pins: gbe2-pins {
285 mux {
286 function = "led";
287 groups = "gbe2_led0";
288 };
289 };
290
291 gbe3_led0_pins: gbe3-pins {
292 mux {
293 function = "led";
294 groups = "gbe3_led0";
295 };
296 };
297
298 i2p5gbe_led0_pins: 2p5gbe-pins {
299 mux {
300 function = "led";
301 groups = "2p5gbe_led0";
302 };
303 };
304 };
305
306 sgmiisys0: syscon@10060000 {
307 compatible = "mediatek,mt7988-sgmiisys",
308 "mediatek,mt7988-sgmiisys_0",
309 "syscon";
310 reg = <0 0x10060000 0 0x1000>;
311 #clock-cells = <1>;
312 };
313
314 sgmiisys1: syscon@10070000 {
315 compatible = "mediatek,mt7988-sgmiisys",
316 "mediatek,mt7988-sgmiisys_1",
317 "syscon";
318 reg = <0 0x10070000 0 0x1000>;
319 #clock-cells = <1>;
320 };
321
322 usxgmiisys0: usxgmiisys@10080000 {
323 compatible = "mediatek,mt7988-usxgmiisys",
324 "mediatek,mt7988-usxgmiisys_0",
325 "syscon";
326 reg = <0 0x10080000 0 0x1000>;
327 #clock-cells = <1>;
328 };
329
330 usxgmiisys1: usxgmiisys@10081000 {
331 compatible = "mediatek,mt7988-usxgmiisys",
332 "mediatek,mt7988-usxgmiisys_1",
333 "syscon";
334 reg = <0 0x10081000 0 0x1000>;
335 #clock-cells = <1>;
336 };
337
338 xfi_pextp0: xfi_pextp@11f20000 {
339 compatible = "mediatek,mt7988-xfi_pextp",
340 "mediatek,mt7988-xfi_pextp_0",
341 "syscon";
342 reg = <0 0x11f20000 0 0x10000>;
343 #clock-cells = <1>;
344 };
345
346 xfi_pextp1: xfi_pextp@11f30000 {
347 compatible = "mediatek,mt7988-xfi_pextp",
348 "mediatek,mt7988-xfi_pextp_1",
349 "syscon";
350 reg = <0 0x11f30000 0 0x10000>;
351 #clock-cells = <1>;
352 };
353
354 xfi_pll: xfi_pll@11f40000 {
355 compatible = "mediatek,mt7988-xfi_pll", "syscon";
356 reg = <0 0x11f40000 0 0x1000>;
357 #clock-cells = <1>;
358 };
359
360 mcusys: mcusys@100e0000 {
361 compatible = "mediatek,mt7988-mcusys", "syscon";
362 reg = <0 0x100e0000 0 0x1000>;
363 #clock-cells = <1>;
364 };
365
366 uart0: serial@11000000 {
367 compatible = "mediatek,mt7986-uart",
368 "mediatek,mt6577-uart";
369 reg = <0 0x11000000 0 0x100>;
370 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
371 /*
372 * 8250-mtk driver don't control "baud" clock since commit
373 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
374 * still need to be passed to the driver to prevent probe fail
375 */
376 clocks = <&topckgen CLK_TOP_UART_SEL>,
377 <&infracfg CLK_INFRA_52M_UART0_CK>;
378 clock-names = "baud", "bus";
379 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
380 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
381 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
382 <&topckgen CLK_TOP_UART_SEL>;
383 status = "disabled";
384 };
385
386 i2c0: i2c@11003000 {
387 compatible = "mediatek,mt7988-i2c",
388 "mediatek,mt7981-i2c";
389 reg = <0 0x11003000 0 0x1000>,
390 <0 0x10217080 0 0x80>;
391 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
392 clock-div = <1>;
393 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
394 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
395 clock-names = "main", "dma";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 status = "disabled";
399 };
400
401 i2c1: i2c@11004000 {
402 compatible = "mediatek,mt7988-i2c",
403 "mediatek,mt7981-i2c";
404 reg = <0 0x11004000 0 0x1000>,
405 <0 0x10217100 0 0x80>;
406 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
407 clock-div = <1>;
408 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
409 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
410 clock-names = "main", "dma";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 status = "disabled";
414 };
415
416 i2c2: i2c@11005000 {
417 compatible = "mediatek,mt7988-i2c",
418 "mediatek,mt7981-i2c";
419 reg = <0 0x11005000 0 0x1000>,
420 <0 0x10217180 0 0x80>;
421 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
422 clock-div = <1>;
423 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
424 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
425 clock-names = "main", "dma";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 status = "disabled";
429 };
430
431 spi0: spi@11007000 {
432 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
433 reg = <0 0x11007000 0 0x100>;
434 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&topckgen CLK_TOP_MPLL_D2>,
436 <&topckgen CLK_TOP_SPI_SEL>,
437 <&infracfg CLK_INFRA_104M_SPI0>,
438 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
439 clock-names = "parent-clk", "sel-clk", "spi-clk",
440 "spi-hclk";
441
442 #address-cells = <1>;
443 #size-cells = <0>;
444
445 status = "disabled";
446 };
447
448 pcie2: pcie@11280000 {
449 compatible = "mediatek,mt7988-pcie",
450 "mediatek,mt7986-pcie",
451 "mediatek,mt8192-pcie";
452 device_type = "pci";
453 #address-cells = <3>;
454 #size-cells = <2>;
455 reg = <0 0x11280000 0 0x2000>;
456 reg-names = "pcie-mac";
457 linux,pci-domain = <3>;
458 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
459 bus-range = <0x00 0xff>;
460 ranges = <0x81000000 0x00 0x20000000 0x00
461 0x20000000 0x00 0x00200000>,
462 <0x82000000 0x00 0x20200000 0x00
463 0x20200000 0x00 0x07e00000>;
464 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
465 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
466 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
467 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
468 clock-names = "pl_250m", "tl_26m", "peri_26m",
469 "top_133m";
470 status = "disabled";
471
472 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
473 phy-names = "pcie-phy";
474
475 #interrupt-cells = <1>;
476 interrupt-map-mask = <0 0 0 0x7>;
477 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
478 <0 0 0 2 &pcie_intc2 1>,
479 <0 0 0 3 &pcie_intc2 2>,
480 <0 0 0 4 &pcie_intc2 3>;
481 pcie_intc2: interrupt-controller {
482 #address-cells = <0>;
483 #interrupt-cells = <1>;
484 interrupt-controller;
485 };
486 };
487
488 pcie3: pcie@11290000 {
489 compatible = "mediatek,mt7988-pcie",
490 "mediatek,mt7986-pcie",
491 "mediatek,mt8192-pcie";
492 device_type = "pci";
493 #address-cells = <3>;
494 #size-cells = <2>;
495 reg = <0 0x11290000 0 0x2000>;
496 reg-names = "pcie-mac";
497 linux,pci-domain = <2>;
498 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
499 bus-range = <0x00 0xff>;
500 ranges = <0x81000000 0x00 0x28000000 0x00
501 0x28000000 0x00 0x00200000>,
502 <0x82000000 0x00 0x28200000 0x00
503 0x28200000 0x00 0x07e00000>;
504 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
505 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
506 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
507 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
508 clock-names = "pl_250m", "tl_26m", "peri_26m",
509 "top_133m";
510 status = "disabled";
511
512 #interrupt-cells = <1>;
513 interrupt-map-mask = <0 0 0 0x7>;
514 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
515 <0 0 0 2 &pcie_intc3 1>,
516 <0 0 0 3 &pcie_intc3 2>,
517 <0 0 0 4 &pcie_intc3 3>;
518 pcie_intc3: interrupt-controller {
519 #address-cells = <0>;
520 #interrupt-cells = <1>;
521 interrupt-controller;
522 };
523 };
524
525 pcie0: pcie@11300000 {
526 compatible = "mediatek,mt7988-pcie",
527 "mediatek,mt7986-pcie",
528 "mediatek,mt8192-pcie";
529 device_type = "pci";
530 #address-cells = <3>;
531 #size-cells = <2>;
532 reg = <0 0x11300000 0 0x2000>;
533 reg-names = "pcie-mac";
534 linux,pci-domain = <0>;
535 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
536 bus-range = <0x00 0xff>;
537 ranges = <0x81000000 0x00 0x30000000 0x00
538 0x30000000 0x00 0x00200000>,
539 <0x82000000 0x00 0x30200000 0x00
540 0x30200000 0x00 0x07e00000>;
541 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
542 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
543 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
544 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
545 clock-names = "pl_250m", "tl_26m", "peri_26m",
546 "top_133m";
547 status = "disabled";
548
549 #interrupt-cells = <1>;
550 interrupt-map-mask = <0 0 0 0x7>;
551 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
552 <0 0 0 2 &pcie_intc0 1>,
553 <0 0 0 3 &pcie_intc0 2>,
554 <0 0 0 4 &pcie_intc0 3>;
555 pcie_intc0: interrupt-controller {
556 #address-cells = <0>;
557 #interrupt-cells = <1>;
558 interrupt-controller;
559 };
560 };
561
562 pcie1: pcie@11310000 {
563 compatible = "mediatek,mt7988-pcie",
564 "mediatek,mt7986-pcie",
565 "mediatek,mt8192-pcie";
566 device_type = "pci";
567 #address-cells = <3>;
568 #size-cells = <2>;
569 reg = <0 0x11310000 0 0x2000>;
570 reg-names = "pcie-mac";
571 linux,pci-domain = <1>;
572 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
573 bus-range = <0x00 0xff>;
574 ranges = <0x81000000 0x00 0x38000000 0x00
575 0x38000000 0x00 0x00200000>,
576 <0x82000000 0x00 0x38200000 0x00
577 0x38200000 0x00 0x07e00000>;
578 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
579 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
580 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
581 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
582 clock-names = "pl_250m", "tl_26m", "peri_26m",
583 "top_133m";
584 status = "disabled";
585
586 #interrupt-cells = <1>;
587 interrupt-map-mask = <0 0 0 0x7>;
588 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
589 <0 0 0 2 &pcie_intc1 1>,
590 <0 0 0 3 &pcie_intc1 2>,
591 <0 0 0 4 &pcie_intc1 3>;
592 pcie_intc1: interrupt-controller {
593 #address-cells = <0>;
594 #interrupt-cells = <1>;
595 interrupt-controller;
596 };
597 };
598
599 ssusb0: usb@11190000 {
600 compatible = "mediatek,mt7988-xhci",
601 "mediatek,mtk-xhci";
602 reg = <0 0x11190000 0 0x2e00>,
603 <0 0x11193e00 0 0x0100>;
604 reg-names = "mac", "ippc";
605 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
606 phys = <&xphyu2port0 PHY_TYPE_USB2>,
607 <&xphyu3port0 PHY_TYPE_USB3>;
608 clocks = <&infracfg CLK_INFRA_USB_SYS>,
609 <&infracfg CLK_INFRA_USB_XHCI>,
610 <&infracfg CLK_INFRA_USB_REF>,
611 <&infracfg CLK_INFRA_66M_USB_HCK>,
612 <&infracfg CLK_INFRA_133M_USB_HCK>;
613 clock-names = "sys_ck",
614 "xhci_ck",
615 "ref_ck",
616 "mcu_ck",
617 "dma_ck";
618 #address-cells = <2>;
619 #size-cells = <2>;
620 mediatek,p0_speed_fixup;
621 status = "disabled";
622 };
623
624 ssusb1: usb@11200000 {
625 compatible = "mediatek,mt7988-xhci",
626 "mediatek,mtk-xhci";
627 reg = <0 0x11200000 0 0x2e00>,
628 <0 0x11203e00 0 0x0100>;
629 reg-names = "mac", "ippc";
630 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
631 phys = <&tphyu2port0 PHY_TYPE_USB2>,
632 <&tphyu3port0 PHY_TYPE_USB3>;
633 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
634 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
635 <&infracfg CLK_INFRA_USB_CK_P1>,
636 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
637 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
638 clock-names = "sys_ck",
639 "xhci_ck",
640 "ref_ck",
641 "mcu_ck",
642 "dma_ck";
643 #address-cells = <2>;
644 #size-cells = <2>;
645 status = "disabled";
646 };
647
648 tphy: tphy@11c50000 {
649 compatible = "mediatek,mt7988",
650 "mediatek,generic-tphy-v2";
651 #address-cells = <2>;
652 #size-cells = <2>;
653 ranges;
654 status = "disabled";
655 tphyu2port0: usb-phy@11c50000 {
656 reg = <0 0x11c50000 0 0x700>;
657 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
658 clock-names = "ref";
659 #phy-cells = <1>;
660 };
661 tphyu3port0: usb-phy@11c50700 {
662 reg = <0 0x11c50700 0 0x900>;
663 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
664 clock-names = "ref";
665 #phy-cells = <1>;
666 mediatek,usb3-pll-ssc-delta;
667 mediatek,usb3-pll-ssc-delta1;
668 };
669 };
670
671 topmisc: topmisc@11d10000 {
672 compatible = "mediatek,mt7988-topmisc", "syscon",
673 "mediatek,mt7988-power-controller";
674 reg = <0 0x11d10000 0 0x10000>;
675 #clock-cells = <1>;
676 #power-domain-cells = <1>;
677 #address-cells = <1>;
678 #size-cells = <0>;
679 };
680
681 xphy: xphy@11e10000 {
682 compatible = "mediatek,mt7988",
683 "mediatek,xsphy";
684 #address-cells = <2>;
685 #size-cells = <2>;
686 ranges;
687 status = "disabled";
688
689 xphyu2port0: usb-phy@11e10000 {
690 reg = <0 0x11e10000 0 0x400>;
691 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
692 clock-names = "ref";
693 #phy-cells = <1>;
694 };
695
696 xphyu3port0: usb-phy@11e13000 {
697 reg = <0 0x11e13400 0 0x500>;
698 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
699 clock-names = "ref";
700 #phy-cells = <1>;
701 mediatek,syscon-type = <&topmisc 0x218 0>;
702 };
703 };
704
705 efuse: efuse@11f50000 {
706 compatible = "mediatek,efuse";
707 reg = <0 0x11f50000 0 0x1000>;
708 #address-cells = <1>;
709 #size-cells = <1>;
710
711 lvts_calibration: calib@918 {
712 reg = <0x918 0x28>;
713 };
714 phy_calibration_p0: calib@940 {
715 reg = <0x940 0x10>;
716 };
717 phy_calibration_p1: calib@954 {
718 reg = <0x954 0x10>;
719 };
720 phy_calibration_p2: calib@968 {
721 reg = <0x968 0x10>;
722 };
723 phy_calibration_p3: calib@97c {
724 reg = <0x97c 0x10>;
725 };
726 cpufreq_calibration: calib@278 {
727 reg = <0x278 0x1>;
728 };
729 };
730
731 ethsys: syscon@15000000 {
732 #address-cells = <1>;
733 #size-cells = <1>;
734 compatible = "mediatek,mt7988-ethsys", "syscon";
735 reg = <0 0x15000000 0 0x1000>;
736 #clock-cells = <1>;
737 #reset-cells = <1>;
738 };
739
740 switch: switch@15020000 {
741 #address-cells = <1>;
742 #size-cells = <1>;
743 compatible = "mediatek,mt7988-switch";
744 reg = <0 0x15020000 0 0x8000>;
745 interrupt-controller;
746 #interrupt-cells = <1>;
747 interrupt-parent = <&gic>;
748 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
749 resets = <&ethrst 0>;
750 };
751
752 ethwarp: syscon@15031000 {
753 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
754 reg = <0 0x15031000 0 0x1000>;
755 #clock-cells = <1>;
756
757 ethrst: reset-controller {
758 compatible = "ti,syscon-reset";
759 #reset-cells = <1>;
760 ti,reset-bits = <
761 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
762 >;
763 };
764 };
765
766 eth: ethernet@15100000 {
767 compatible = "mediatek,mt7988-eth";
768 reg = <0 0x15100000 0 0x80000>,
769 <0 0x15400000 0 0x380000>;
770 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
775 <&ethsys CLK_ETHDMA_XGP2_EN>,
776 <&ethsys CLK_ETHDMA_XGP3_EN>,
777 <&ethsys CLK_ETHDMA_FE_EN>,
778 <&ethsys CLK_ETHDMA_GP2_EN>,
779 <&ethsys CLK_ETHDMA_GP1_EN>,
780 <&ethsys CLK_ETHDMA_GP3_EN>,
781 <&ethsys CLK_ETHDMA_ESW_EN>,
782 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
783 <&sgmiisys0 CLK_SGM0_TX_EN>,
784 <&sgmiisys0 CLK_SGM0_RX_EN>,
785 <&sgmiisys1 CLK_SGM1_TX_EN>,
786 <&sgmiisys1 CLK_SGM1_RX_EN>,
787 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
788 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
789 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
790 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
791 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
792 <&topckgen CLK_TOP_SGM_0_SEL>,
793 <&topckgen CLK_TOP_SGM_1_SEL>,
794 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
795 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
796 <&topckgen CLK_TOP_ETH_GMII_SEL>,
797 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
798 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
799 <&topckgen CLK_TOP_ETH_SYS_SEL>,
800 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
801 <&topckgen CLK_TOP_ETH_MII_SEL>,
802 <&topckgen CLK_TOP_NETSYS_SEL>,
803 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
804 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
805 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
806 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
807 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
808 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
809 "gp3", "esw", "crypto", "sgmii_tx250m",
810 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
811 "ethwarp_wocpu2", "ethwarp_wocpu1",
812 "ethwarp_wocpu0", "top_usxgmii0_sel",
813 "top_usxgmii1_sel", "top_sgm0_sel",
814 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
815 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
816 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
817 "top_eth_sys_sel", "top_eth_xgmii_sel",
818 "top_eth_mii_sel", "top_netsys_sel",
819 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
820 "top_netsys_sync_250m_sel",
821 "top_netsys_ppefb_250m_sel",
822 "top_netsys_warp_sel";
823 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
824 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
825 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
826 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
827 <&topckgen CLK_TOP_SGM_0_SEL>,
828 <&topckgen CLK_TOP_SGM_1_SEL>;
829 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
830 <&topckgen CLK_TOP_NET1PLL_D4>,
831 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
832 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
833 <&apmixedsys CLK_APMIXED_SGMPLL>,
834 <&apmixedsys CLK_APMIXED_SGMPLL>;
835 mediatek,ethsys = <&ethsys>;
836 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
837 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
838 mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
839 mediatek,xfi_pll = <&xfi_pll>;
840 mediatek,infracfg = <&topmisc>;
841 mediatek,toprgu = <&watchdog>;
842 #reset-cells = <1>;
843 #address-cells = <1>;
844 #size-cells = <0>;
845 status = "disabled";
846 };
847 };
848 };
Staging tree of Stijn Tintel