target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2023 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/pinctrl/mt65xx.h>
  13 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15
  16 /* TOPRGU resets */
  17 #define MT7988_TOPRGU_SGMII0_GRST               1
  18 #define MT7988_TOPRGU_SGMII1_GRST               2
  19 #define MT7988_TOPRGU_XFI0_GRST                 12
  20 #define MT7988_TOPRGU_XFI1_GRST                 13
  21 #define MT7988_TOPRGU_XFI_PEXTP0_GRST           14
  22 #define MT7988_TOPRGU_XFI_PEXTP1_GRST           15
  23 #define MT7988_TOPRGU_XFI_PLL_GRST              16
  24
  25 / {
  26         compatible = "mediatek,mt7988";
  27         interrupt-parent = <&gic>;
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         cci: cci {
  32                 compatible = "mediatek,mt7988-cci",
  33                              "mediatek,mt8183-cci";
  34                 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
  35                          <&topckgen CLK_TOP_XTAL>;
  36                 clock-names = "cci", "intermediate";
  37                 operating-points-v2 = <&cci_opp>;
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 cpu0: cpu@0 {
  45                         compatible = "arm,cortex-a73";
  46                         reg = <0x0>;
  47                         device_type = "cpu";
  48                         enable-method = "psci";
  49                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  50                                  <&topckgen CLK_TOP_XTAL>;
  51                         clock-names = "cpu", "intermediate";
  52                         operating-points-v2 = <&cluster0_opp>;
  53                         mediatek,cci = <&cci>;
  54                 };
  55
  56                 cpu1: cpu@1 {
  57                         compatible = "arm,cortex-a73";
  58                         reg = <0x1>;
  59                         device_type = "cpu";
  60                         enable-method = "psci";
  61                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  62                                  <&topckgen CLK_TOP_XTAL>;
  63                         clock-names = "cpu", "intermediate";
  64                         operating-points-v2 = <&cluster0_opp>;
  65                         mediatek,cci = <&cci>;
  66                 };
  67
  68                 cpu2: cpu@2 {
  69                         compatible = "arm,cortex-a73";
  70                         reg = <0x2>;
  71                         device_type = "cpu";
  72                         enable-method = "psci";
  73                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  74                                  <&topckgen CLK_TOP_XTAL>;
  75                         clock-names = "cpu", "intermediate";
  76                         operating-points-v2 = <&cluster0_opp>;
  77                         mediatek,cci = <&cci>;
  78                 };
  79
  80                 cpu3: cpu@3 {
  81                         compatible = "arm,cortex-a73";
  82                         reg = <0x3>;
  83                         device_type = "cpu";
  84                         enable-method = "psci";
  85                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  86                                  <&topckgen CLK_TOP_XTAL>;
  87                         clock-names = "cpu", "intermediate";
  88                         operating-points-v2 = <&cluster0_opp>;
  89                         mediatek,cci = <&cci>;
  90                 };
  91
  92                 cluster0_opp: opp_table0 {
  93                         compatible = "operating-points-v2";
  94                         opp-shared;
  95
  96                         opp00 {
  97                                 opp-hz = /bits/ 64 <800000000>;
  98                                 opp-microvolt = <850000>;
  99                         };
 100
 101                         opp01 {
 102                                 opp-hz = /bits/ 64 <1100000000>;
 103                                 opp-microvolt = <850000>;
 104                         };
 105
 106                         opp02 {
 107                                 opp-hz = /bits/ 64 <1500000000>;
 108                                 opp-microvolt = <850000>;
 109                         };
 110
 111                         opp03 {
 112                                 opp-hz = /bits/ 64 <1800000000>;
 113                                 opp-microvolt = <900000>;
 114                         };
 115                 };
 116         };
 117
 118         cci_opp: opp_table_cci {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121
 122                 opp00 {
 123                         opp-hz = /bits/ 64 <480000000>;
 124                         opp-microvolt = <850000>;
 125                 };
 126
 127                 opp01 {
 128                         opp-hz = /bits/ 64 <660000000>;
 129                         opp-microvolt = <850000>;
 130                 };
 131
 132                 opp02 {
 133                         opp-hz = /bits/ 64 <900000000>;
 134                         opp-microvolt = <850000>;
 135                 };
 136
 137                 opp03 {
 138                         opp-hz = /bits/ 64 <1080000000>;
 139                         opp-microvolt = <900000>;
 140                 };
 141         };
 142
 143         clk40m: oscillator@0 {
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <40000000>;
 146                 #clock-cells = <0>;
 147                 clock-output-names = "clkxtal";
 148         };
 149
 150         fan: pwm-fan {
 151                 compatible = "pwm-fan";
 152                 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
 153                 cooling-levels = <0 128 255>;
 154                 #cooling-cells = <2>;
 155                 #thermal-sensor-cells = <1>;
 156                 status = "disabled";
 157         };
 158
 159         pmu {
 160                 compatible = "arm,cortex-a73-pmu";
 161                 interrupt-parent = <&gic>;
 162                 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 163         };
 164
 165         psci {
 166                 compatible = "arm,psci-0.2";
 167                 method = "smc";
 168         };
 169
 170         reg_1p8v: regulator-1p8v {
 171                 compatible = "regulator-fixed";
 172                 regulator-name = "fixed-1.8V";
 173                 regulator-min-microvolt = <1800000>;
 174                 regulator-max-microvolt = <1800000>;
 175                 regulator-boot-on;
 176                 regulator-always-on;
 177         };
 178
 179         reg_3p3v: regulator-3p3v {
 180                 compatible = "regulator-fixed";
 181                 regulator-name = "fixed-3.3V";
 182                 regulator-min-microvolt = <3300000>;
 183                 regulator-max-microvolt = <3300000>;
 184                 regulator-boot-on;
 185                 regulator-always-on;
 186         };
 187
 188         reserved-memory {
 189                 ranges;
 190                 #address-cells = <2>;
 191                 #size-cells = <2>;
 192
 193                 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
 194                 secmon_reserved: secmon@43000000 {
 195                         reg = <0 0x43000000 0 0x50000>;
 196                         no-map;
 197                 };
 198         };
 199
 200         soc {
 201                 compatible = "simple-bus";
 202                 ranges;
 203                 #address-cells = <2>;
 204                 #size-cells = <2>;
 205
 206                 gic: interrupt-controller@c000000 {
 207                         compatible = "arm,gic-v3";
 208                         reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 209                               <0 0x0c080000 0 0x200000>, /* GICR */
 210                               <0 0x0c400000 0 0x2000>,   /* GICC */
 211                               <0 0x0c410000 0 0x1000>,   /* GICH */
 212                               <0 0x0c420000 0 0x2000>;   /* GICV */
 213                         interrupt-parent = <&gic>;
 214                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <3>;
 217                 };
 218
 219                 phyfw: phy-firmware@f000000 {
 220                         compatible = "mediatek,2p5gphy-fw";
 221                         reg = <0 0x0f000000 0 0x8000>,
 222                               <0 0x0f100000 0 0x20000>,
 223                               <0 0x0f0f0000 0 0x200>;
 224                 };
 225
 226                 infracfg: infracfg@10001000 {
 227                         compatible = "mediatek,mt7988-infracfg", "syscon";
 228                         reg = <0 0x10001000 0 0x1000>;
 229                         #clock-cells = <1>;
 230                         #reset-cells = <1>;
 231                 };
 232
 233                 topckgen: topckgen@1001b000 {
 234                         compatible = "mediatek,mt7988-topckgen", "syscon";
 235                         reg = <0 0x1001b000 0 0x1000>;
 236                         #clock-cells = <1>;
 237                 };
 238
 239                 watchdog: watchdog@1001c000 {
 240                         compatible = "mediatek,mt7988-wdt",
 241                                      "mediatek,mt6589-wdt",
 242                                      "syscon";
 243                         reg = <0 0x1001c000 0 0x1000>;
 244                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 245                         #reset-cells = <1>;
 246                 };
 247
 248                 apmixedsys: apmixedsys@1001e000 {
 249                         compatible = "mediatek,mt7988-apmixedsys";
 250                         reg = <0 0x1001e000 0 0x1000>;
 251                         #clock-cells = <1>;
 252                 };
 253
 254                 pio: pinctrl@1001f000 {
 255                         compatible = "mediatek,mt7988-pinctrl", "syscon";
 256                         reg = <0 0x1001f000 0 0x1000>,
 257                               <0 0x11c10000 0 0x1000>,
 258                               <0 0x11d00000 0 0x1000>,
 259                               <0 0x11d20000 0 0x1000>,
 260                               <0 0x11e00000 0 0x1000>,
 261                               <0 0x11f00000 0 0x1000>,
 262                               <0 0x1000b000 0 0x1000>;
 263                         reg-names = "gpio_base", "iocfg_tr_base",
 264                                     "iocfg_br_base", "iocfg_rb_base",
 265                                     "iocfg_lb_base", "iocfg_tl_base", "eint";
 266                         gpio-controller;
 267                         #gpio-cells = <2>;
 268                         gpio-ranges = <&pio 0 0 84>;
 269                         interrupt-controller;
 270                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 271                         interrupt-parent = <&gic>;
 272                         #interrupt-cells = <2>;
 273
 274                         mdio0_pins: mdio0-pins {
 275                                 mux {
 276                                         function = "eth";
 277                                         groups = "mdc_mdio0";
 278                                 };
 279
 280                                 conf {
 281                                         groups = "mdc_mdio0";
 282                                         drive-strength = <MTK_DRIVE_8mA>;
 283                                 };
 284                         };
 285
 286                         i2c0_pins: i2c0-pins-g0 {
 287                                 mux {
 288                                         function = "i2c";
 289                                         groups = "i2c0_1";
 290                                 };
 291                         };
 292
 293                         i2c1_pins: i2c1-pins-g0 {
 294                                 mux {
 295                                         function = "i2c";
 296                                         groups = "i2c1_0";
 297                                 };
 298                         };
 299
 300                         i2c1_sfp_pins: i2c1-sfp-pins-g0 {
 301                                 mux {
 302                                         function = "i2c";
 303                                         groups = "i2c1_sfp";
 304                                 };
 305                         };
 306
 307                         i2c2_pins: i2c2-pins {
 308                                 mux {
 309                                         function = "i2c";
 310                                         groups = "i2c2";
 311                                 };
 312                         };
 313
 314                         i2c2_0_pins: i2c2-pins-g0 {
 315                                 mux {
 316                                         function = "i2c";
 317                                         groups = "i2c2_0";
 318                                 };
 319                         };
 320
 321                         i2c2_1_pins: i2c2-pins-g1 {
 322                                 mux {
 323                                         function = "i2c";
 324                                         groups = "i2c2_1";
 325                                 };
 326                         };
 327
 328                         gbe0_led0_pins: gbe0-led0-pins {
 329                                 mux {
 330                                         function = "led";
 331                                         groups = "gbe0_led0";
 332                                 };
 333                         };
 334
 335                         gbe1_led0_pins: gbe1-led0-pins {
 336                                 mux {
 337                                         function = "led";
 338                                         groups = "gbe1_led0";
 339                                 };
 340                         };
 341
 342                         gbe2_led0_pins: gbe2-led0-pins {
 343                                 mux {
 344                                         function = "led";
 345                                         groups = "gbe2_led0";
 346                                 };
 347                         };
 348
 349                         gbe3_led0_pins: gbe3-led0-pins {
 350                                 mux {
 351                                         function = "led";
 352                                         groups = "gbe3_led0";
 353                                 };
 354                         };
 355
 356                         gbe0_led1_pins: gbe0-led1-pins {
 357                                 mux {
 358                                         function = "led";
 359                                         groups = "gbe0_led1";
 360                                 };
 361                         };
 362
 363                         gbe1_led1_pins: gbe1-led1-pins {
 364                                 mux {
 365                                         function = "led";
 366                                         groups = "gbe1_led1";
 367                                 };
 368                         };
 369
 370                         gbe2_led1_pins: gbe2-led1-pins {
 371                                 mux {
 372                                         function = "led";
 373                                         groups = "gbe2_led1";
 374                                 };
 375                         };
 376
 377                         gbe3_led1_pins: gbe3-led1-pins {
 378                                 mux {
 379                                         function = "led";
 380                                         groups = "gbe3_led1";
 381                                 };
 382                         };
 383
 384                         i2p5gbe_led0_pins: 2p5gbe-led0-pins {
 385                                 mux {
 386                                         function = "led";
 387                                         groups = "2p5gbe_led0";
 388                                 };
 389                         };
 390
 391                         i2p5gbe_led1_pins: 2p5gbe-led1-pins {
 392                                 mux {
 393                                         function = "led";
 394                                         groups = "2p5gbe_led1";
 395                                 };
 396                         };
 397
 398                         mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
 399                                 mux {
 400                                         function = "flash";
 401                                         groups = "emmc_45";
 402                                 };
 403                         };
 404
 405                         mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
 406                                 mux {
 407                                         function = "flash";
 408                                         groups = "emmc_51";
 409                                 };
 410                         };
 411
 412                         mmc0_pins_sdcard: mmc0-pins-sdcard {
 413                                 mux {
 414                                         function = "flash";
 415                                         groups = "sdcard";
 416                                 };
 417                         };
 418
 419                         uart0_pins: uart0-pins {
 420                                 mux {
 421                                         function = "uart";
 422                                         groups =  "uart0";
 423                                 };
 424                         };
 425
 426                         uart1_0_pins: uart1-0-pins {
 427                                 mux {
 428                                         function = "uart";
 429                                         groups =  "uart1_0";
 430                                 };
 431                         };
 432
 433                         uart1_1_pins: uart1-1-pins {
 434                                 mux {
 435                                         function = "uart";
 436                                         groups =  "uart1_1";
 437                                 };
 438                         };
 439
 440                         uart1_2_pins: uart1-2-pins {
 441                                 mux {
 442                                         function = "uart";
 443                                         groups =  "uart1_2";
 444                                 };
 445                         };
 446
 447                         uart1_2_lite_pins: uart1-2-lite-pins {
 448                                 mux {
 449                                         function = "uart";
 450                                         groups =  "uart1_2_lite";
 451                                 };
 452                         };
 453
 454                         uart2_pins: uart2-pins {
 455                                 mux {
 456                                         function = "uart";
 457                                         groups =  "uart2";
 458                                 };
 459                         };
 460
 461                         uart2_0_pins: uart2-0-pins {
 462                                 mux {
 463                                         function = "uart";
 464                                         groups =  "uart2_0";
 465                                 };
 466                         };
 467
 468                         uart2_1_pins: uart2-1-pins {
 469                                 mux {
 470                                         function = "uart";
 471                                         groups =  "uart2_1";
 472                                 };
 473                         };
 474
 475                         uart2_2_pins: uart2-2-pins {
 476                                 mux {
 477                                         function = "uart";
 478                                         groups =  "uart2_2";
 479                                 };
 480                         };
 481
 482                         uart2_3_pins: uart2-3-pins {
 483                                 mux {
 484                                         function = "uart";
 485                                         groups =  "uart2_3";
 486                                 };
 487                         };
 488
 489                         snfi_pins: snfi-pins {
 490                                 mux {
 491                                         function = "flash";
 492                                         groups = "snfi";
 493                                 };
 494                         };
 495
 496                         spi0_pins: spi0-pins {
 497                                 mux {
 498                                         function = "spi";
 499                                         groups = "spi0";
 500                                 };
 501                         };
 502
 503                         spi0_flash_pins: spi0-flash-pins {
 504                                 mux {
 505                                         function = "spi";
 506                                         groups = "spi0", "spi0_wp_hold";
 507                                 };
 508                         };
 509
 510                         spi1_pins: spi1-pins {
 511                                 mux {
 512                                         function = "spi";
 513                                         groups = "spi1";
 514                                 };
 515                         };
 516
 517                         spi2_pins: spi2-pins {
 518                                 mux {
 519                                         function = "spi";
 520                                         groups = "spi2";
 521                                 };
 522                         };
 523
 524                         spi2_flash_pins: spi2-flash-pins {
 525                                 mux {
 526                                         function = "spi";
 527                                         groups = "spi2", "spi2_wp_hold";
 528                                 };
 529                         };
 530
 531                         pcie0_pins: pcie0-pins {
 532                                 mux {
 533                                         function = "pcie";
 534                                         groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
 535                                                  "pcie_wake_n0_0";
 536                                 };
 537                         };
 538
 539                         pcie1_pins: pcie1-pins {
 540                                 mux {
 541                                         function = "pcie";
 542                                         groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
 543                                                  "pcie_wake_n1_0";
 544                                 };
 545                         };
 546
 547                         pcie2_pins: pcie2-pins {
 548                                 mux {
 549                                         function = "pcie";
 550                                         groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
 551                                                  "pcie_wake_n2_0";
 552                                 };
 553                         };
 554
 555                         pcie3_pins: pcie3-pins {
 556                                 mux {
 557                                         function = "pcie";
 558                                         groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
 559                                                  "pcie_wake_n3_0";
 560                                 };
 561                         };
 562                 };
 563
 564                 pwm: pwm@10048000 {
 565                         compatible = "mediatek,mt7988-pwm";
 566                         reg = <0 0x10048000 0 0x1000>;
 567                         #pwm-cells = <2>;
 568                         clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
 569                                  <&infracfg CLK_INFRA_66M_PWM_HCK>,
 570                                  <&infracfg CLK_INFRA_66M_PWM_CK1>,
 571                                  <&infracfg CLK_INFRA_66M_PWM_CK2>,
 572                                  <&infracfg CLK_INFRA_66M_PWM_CK3>,
 573                                  <&infracfg CLK_INFRA_66M_PWM_CK4>,
 574                                  <&infracfg CLK_INFRA_66M_PWM_CK5>,
 575                                  <&infracfg CLK_INFRA_66M_PWM_CK6>,
 576                                  <&infracfg CLK_INFRA_66M_PWM_CK7>,
 577                                  <&infracfg CLK_INFRA_66M_PWM_CK8>;
 578                         clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
 579                                       "pwm4","pwm5","pwm6","pwm7","pwm8";
 580                         status = "disabled";
 581                 };
 582
 583                 sgmiisys0: syscon@10060000 {
 584                         compatible = "mediatek,mt7988-sgmiisys",
 585                                      "mediatek,mt7988-sgmiisys0",
 586                                      "syscon",
 587                                      "simple-mfd";
 588                         reg = <0 0x10060000 0 0x1000>;
 589                         resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
 590                         #clock-cells = <1>;
 591
 592                         sgmiipcs0: pcs {
 593                                 compatible = "mediatek,mt7988-sgmii";
 594                                 clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
 595                                          <&sgmiisys0 CLK_SGM0_TX_EN>,
 596                                          <&sgmiisys0 CLK_SGM0_RX_EN>;
 597                                 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
 598                         };
 599                 };
 600
 601                 sgmiisys1: syscon@10070000 {
 602                         compatible = "mediatek,mt7988-sgmiisys",
 603                                      "mediatek,mt7988-sgmiisys1",
 604                                      "syscon",
 605                                      "simple-mfd";
 606                         reg = <0 0x10070000 0 0x1000>;
 607                         resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
 608                         #clock-cells = <1>;
 609
 610                         sgmiipcs1: pcs {
 611                                 compatible = "mediatek,mt7988-sgmii";
 612                                 clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
 613                                          <&sgmiisys1 CLK_SGM1_TX_EN>,
 614                                          <&sgmiisys1 CLK_SGM1_RX_EN>;
 615                                 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
 616                         };
 617                 };
 618
 619                 usxgmiisys0: pcs@10080000 {
 620                         compatible = "mediatek,mt7988-usxgmiisys";
 621                         reg = <0 0x10080000 0 0x1000>;
 622                         resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
 623                         clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
 624                 };
 625
 626                 usxgmiisys1: pcs@10081000 {
 627                         compatible = "mediatek,mt7988-usxgmiisys";
 628                         reg = <0 0x10081000 0 0x1000>;
 629                         resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
 630                         clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
 631                 };
 632
 633                 mcusys: mcusys@100e0000 {
 634                         compatible = "mediatek,mt7988-mcusys", "syscon";
 635                         reg = <0 0x100e0000 0 0x1000>;
 636                         #clock-cells = <1>;
 637                 };
 638
 639                 uart0: serial@11000000 {
 640                         compatible = "mediatek,mt7986-uart",
 641                                      "mediatek,mt6577-uart";
 642                         reg = <0 0x11000000 0 0x100>;
 643                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 644                         /*
 645                          * 8250-mtk driver don't control "baud" clock since commit
 646                          * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
 647                          * still need to be passed to the driver to prevent probe fail
 648                          */
 649                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 650                                  <&infracfg CLK_INFRA_52M_UART0_CK>;
 651                         clock-names = "baud", "bus";
 652                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 653                                           <&infracfg CLK_INFRA_MUX_UART0_SEL>;
 654                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 655                                                  <&topckgen CLK_TOP_UART_SEL>;
 656                         pinctrl-names = "default";
 657                         pinctrl-0 = <&uart0_pins>;
 658                         status = "disabled";
 659                 };
 660
 661                 uart1: serial@11000100 {
 662                         compatible = "mediatek,mt7986-uart",
 663                                      "mediatek,mt6577-uart";
 664                         reg = <0 0x11000100 0 0x100>;
 665                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 666                         /*
 667                          * 8250-mtk driver don't control "baud" clock since commit
 668                          * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
 669                          * still need to be passed to the driver to prevent probe fail
 670                          */
 671                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 672                                  <&infracfg CLK_INFRA_52M_UART1_CK>;
 673                         clock-names = "baud", "bus";
 674                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 675                                           <&infracfg CLK_INFRA_MUX_UART1_SEL>;
 676                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 677                                                  <&topckgen CLK_TOP_UART_SEL>;
 678                         status = "disabled";
 679                 };
 680
 681                 uart2: serial@11000200 {
 682                         compatible = "mediatek,mt7986-uart",
 683                                      "mediatek,mt6577-uart";
 684                         reg = <0 0x11000200 0 0x100>;
 685                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 686                         /*
 687                          * 8250-mtk driver don't control "baud" clock since commit
 688                          * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
 689                          * still need to be passed to the driver to prevent probe fail
 690                          */
 691                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 692                                  <&infracfg CLK_INFRA_52M_UART2_CK>;
 693                         clock-names = "baud", "bus";
 694                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 695                                           <&infracfg CLK_INFRA_MUX_UART2_SEL>;
 696                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 697                                                  <&topckgen CLK_TOP_UART_SEL>;
 698                         status = "disabled";
 699                 };
 700
 701                 snand: spi@11001000 {
 702                         compatible = "mediatek,mt7986-snand";
 703                         reg = <0 0x11001000 0 0x1000>;
 704                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 705                         clocks = <&infracfg CLK_INFRA_SPINFI>,
 706                                  <&infracfg CLK_INFRA_NFI>;
 707                         clock-names = "pad_clk", "nfi_clk";
 708                         assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 709                                           <&topckgen CLK_TOP_NFI1X_SEL>;
 710                         assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
 711                                                  <&topckgen CLK_TOP_MPLL_D8>;
 712                         nand-ecc-engine = <&bch>;
 713                         mediatek,quad-spi;
 714                         #address-cells = <1>;
 715                         #size-cells = <0>;
 716                         pinctrl-names = "default";
 717                         pinctrl-0 = <&snfi_pins>;
 718                         status = "disabled";
 719                 };
 720
 721                 bch: ecc@11002000 {
 722                         compatible = "mediatek,mt7686-ecc";
 723                         reg = <0 0x11002000 0 0x1000>;
 724                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
 726                         clock-names = "nfiecc_clk";
 727                         status = "disabled";
 728                 };
 729
 730                 i2c0: i2c@11003000 {
 731                         compatible = "mediatek,mt7988-i2c",
 732                                      "mediatek,mt7981-i2c";
 733                         reg = <0 0x11003000 0 0x1000>,
 734                               <0 0x10217080 0 0x80>;
 735                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 736                         clock-div = <1>;
 737                         clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 738                                  <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 739                         clock-names = "main", "dma";
 740                         #address-cells = <1>;
 741                         #size-cells = <0>;
 742                         status = "disabled";
 743                 };
 744
 745                 i2c1: i2c@11004000 {
 746                         compatible = "mediatek,mt7988-i2c",
 747                                      "mediatek,mt7981-i2c";
 748                         reg = <0 0x11004000 0 0x1000>,
 749                               <0 0x10217100 0 0x80>;
 750                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 751                         clock-div = <1>;
 752                         clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 753                                  <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 754                         clock-names = "main", "dma";
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                         status = "disabled";
 758                 };
 759
 760                 i2c2: i2c@11005000 {
 761                         compatible = "mediatek,mt7988-i2c",
 762                                 "mediatek,mt7981-i2c";
 763                         reg = <0 0x11005000 0 0x1000>,
 764                               <0 0x10217180 0 0x80>;
 765                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 766                         clock-div = <1>;
 767                         clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 768                                  <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 769                         clock-names = "main", "dma";
 770                         #address-cells = <1>;
 771                         #size-cells = <0>;
 772                         status = "disabled";
 773                 };
 774
 775                 spi0: spi@11007000 {
 776                         compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
 777                         reg = <0 0x11007000 0 0x100>;
 778                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 780                                  <&topckgen CLK_TOP_SPI_SEL>,
 781                                  <&infracfg CLK_INFRA_104M_SPI0>,
 782                                  <&infracfg CLK_INFRA_66M_SPI0_HCK>;
 783                         clock-names = "parent-clk", "sel-clk", "spi-clk",
 784                                       "spi-hclk";
 785                         #address-cells = <1>;
 786                         #size-cells = <0>;
 787                         status = "disabled";
 788                 };
 789
 790                 spi1: spi@11008000 {
 791                         compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
 792                         reg = <0 0x11008000 0 0x100>;
 793                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 794                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 795                                  <&topckgen CLK_TOP_SPI_SEL>,
 796                                  <&infracfg CLK_INFRA_104M_SPI1>,
 797                                  <&infracfg CLK_INFRA_66M_SPI1_HCK>;
 798                         clock-names = "parent-clk", "sel-clk", "spi-clk",
 799                                       "spi-hclk";
 800                         #address-cells = <1>;
 801                         #size-cells = <0>;
 802                         pinctrl-names = "default";
 803                         pinctrl-0 = <&spi1_pins>;
 804                         status = "disabled";
 805                 };
 806
 807                 spi2: spi@11009000 {
 808                         compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
 809                         reg = <0 0x11009000 0 0x100>;
 810                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 811                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 812                                  <&topckgen CLK_TOP_SPI_SEL>,
 813                                  <&infracfg CLK_INFRA_104M_SPI2_BCK>,
 814                                  <&infracfg CLK_INFRA_66M_SPI2_HCK>;
 815                         clock-names = "parent-clk", "sel-clk", "spi-clk",
 816                                       "spi-hclk";
 817                         #address-cells = <1>;
 818                         #size-cells = <0>;
 819                         status = "disabled";
 820                 };
 821
 822                 lvts: lvts@1100a000 {
 823                         compatible = "mediatek,mt7988-lvts-ap";
 824                         reg = <0 0x1100a000 0 0x1000>;
 825                         clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
 826                         clock-names = "lvts_clk";
 827                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 828                         resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
 829                         nvmem-cells = <&lvts_calibration>;
 830                         nvmem-cell-names = "lvts-calib-data-1";
 831                         #thermal-sensor-cells = <1>;
 832                 };
 833
 834                 ssusb0: usb@11190000 {
 835                         compatible = "mediatek,mt7988-xhci",
 836                                      "mediatek,mtk-xhci";
 837                         reg = <0 0x11190000 0 0x2e00>,
 838                               <0 0x11193e00 0 0x0100>;
 839                         reg-names = "mac", "ippc";
 840                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 841                         phys = <&xphyu2port0 PHY_TYPE_USB2>,
 842                                <&xphyu3port0 PHY_TYPE_USB3>;
 843                         clocks = <&infracfg CLK_INFRA_USB_SYS>,
 844                                  <&infracfg CLK_INFRA_USB_XHCI>,
 845                                  <&infracfg CLK_INFRA_USB_REF>,
 846                                  <&infracfg CLK_INFRA_66M_USB_HCK>,
 847                                  <&infracfg CLK_INFRA_133M_USB_HCK>;
 848                         clock-names = "sys_ck",
 849                                       "xhci_ck",
 850                                       "ref_ck",
 851                                       "mcu_ck",
 852                                       "dma_ck";
 853                         #address-cells = <2>;
 854                         #size-cells = <2>;
 855                         mediatek,p0_speed_fixup;
 856                         status = "disabled";
 857                 };
 858
 859                 ssusb1: usb@11200000 {
 860                         compatible = "mediatek,mt7988-xhci",
 861                                      "mediatek,mtk-xhci";
 862                         reg = <0 0x11200000 0 0x2e00>,
 863                               <0 0x11203e00 0 0x0100>;
 864                         reg-names = "mac", "ippc";
 865                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 866                         phys = <&tphyu2port0 PHY_TYPE_USB2>,
 867                                <&tphyu3port0 PHY_TYPE_USB3>;
 868                         clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
 869                                  <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
 870                                  <&infracfg CLK_INFRA_USB_CK_P1>,
 871                                  <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
 872                                  <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
 873                         clock-names = "sys_ck",
 874                                       "xhci_ck",
 875                                       "ref_ck",
 876                                       "mcu_ck",
 877                                       "dma_ck";
 878                         #address-cells = <2>;
 879                         #size-cells = <2>;
 880                         status = "disabled";
 881                 };
 882
 883                 afe: audio-controller@11210000 {
 884                         compatible = "mediatek,mt79xx-audio";
 885                         reg = <0 0x11210000 0 0x9000>;
 886                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 887                         clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
 888                                  <&infracfg CLK_INFRA_AUD_26M>,
 889                                  <&infracfg CLK_INFRA_AUD_L>,
 890                                  <&infracfg CLK_INFRA_AUD_AUD>,
 891                                  <&infracfg CLK_INFRA_AUD_EG2>,
 892                                  <&topckgen CLK_TOP_AUD_SEL>,
 893                                  <&topckgen CLK_TOP_AUD_I2S_M>;
 894                         clock-names = "aud_bus_ck",
 895                                       "aud_26m_ck",
 896                                       "aud_l_ck",
 897                                       "aud_aud_ck",
 898                                       "aud_eg2_ck",
 899                                       "aud_sel",
 900                                       "aud_i2s_m";
 901                         assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
 902                                           <&topckgen CLK_TOP_A1SYS_SEL>,
 903                                           <&topckgen CLK_TOP_AUD_L_SEL>,
 904                                           <&topckgen CLK_TOP_A_TUNER_SEL>;
 905                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
 906                                                  <&topckgen CLK_TOP_APLL2_D4>,
 907                                                  <&apmixedsys CLK_APMIXED_APLL2>,
 908                                                  <&topckgen CLK_TOP_APLL2_D4>;
 909                         status = "disabled";
 910                 };
 911
 912                 mmc0: mmc@11230000 {
 913                         compatible = "mediatek,mt7986-mmc",
 914                                      "mediatek,mt7981-mmc";
 915                         reg = <0 0x11230000 0 0x1000>,
 916                               <0 0x11D60000 0 0x1000>;
 917                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 918                         clocks = <&infracfg CLK_INFRA_MSDC400>,
 919                                  <&infracfg CLK_INFRA_MSDC2_HCK>,
 920                                  <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
 921                                  <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
 922                         assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
 923                                           <&topckgen CLK_TOP_EMMC_400M_SEL>;
 924                         assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
 925                                                  <&apmixedsys CLK_APMIXED_MSDCPLL>;
 926                         clock-names = "source",
 927                                       "hclk",
 928                                       "axi_cg",
 929                                       "ahb_cg";
 930                         #address-cells = <1>;
 931                         #size-cells = <0>;
 932                         status = "disabled";
 933                 };
 934
 935                 pcie2: pcie@11280000 {
 936                         compatible = "mediatek,mt7988-pcie",
 937                                      "mediatek,mt7986-pcie",
 938                                      "mediatek,mt8192-pcie";
 939                         reg = <0 0x11280000 0 0x2000>;
 940                         reg-names = "pcie-mac";
 941                         ranges = <0x81000000 0x00 0x20000000 0x00
 942                                   0x20000000 0x00 0x00200000>,
 943                                  <0x82000000 0x00 0x20200000 0x00
 944                                   0x20200000 0x00 0x07e00000>;
 945                         device_type = "pci";
 946                         linux,pci-domain = <3>;
 947                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 948                         bus-range = <0x00 0xff>;
 949                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
 950                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
 951                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
 952                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
 953                         clock-names = "pl_250m", "tl_26m", "peri_26m",
 954                                       "top_133m";
 955                         pinctrl-names = "default";
 956                         pinctrl-0 = <&pcie2_pins>;
 957                         phys = <&xphyu3port0 PHY_TYPE_PCIE>;
 958                         phy-names = "pcie-phy";
 959                         #interrupt-cells = <1>;
 960                         interrupt-map-mask = <0 0 0 0x7>;
 961                         interrupt-map = <0 0 0 1 &pcie_intc2 0>,
 962                                         <0 0 0 2 &pcie_intc2 1>,
 963                                         <0 0 0 3 &pcie_intc2 2>,
 964                                         <0 0 0 4 &pcie_intc2 3>;
 965                         #address-cells = <3>;
 966                         #size-cells = <2>;
 967                         status = "disabled";
 968
 969                         pcie_intc2: interrupt-controller {
 970                                 #address-cells = <0>;
 971                                 #interrupt-cells = <1>;
 972                                 interrupt-controller;
 973                         };
 974                 };
 975
 976                 pcie3: pcie@11290000 {
 977                         compatible = "mediatek,mt7988-pcie",
 978                                      "mediatek,mt7986-pcie",
 979                                      "mediatek,mt8192-pcie";
 980                         reg = <0 0x11290000 0 0x2000>;
 981                         reg-names = "pcie-mac";
 982                         ranges = <0x81000000 0x00 0x28000000 0x00
 983                                   0x28000000 0x00 0x00200000>,
 984                                  <0x82000000 0x00 0x28200000 0x00
 985                                   0x28200000 0x00 0x07e00000>;
 986                         device_type = "pci";
 987                         linux,pci-domain = <2>;
 988                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 989                         bus-range = <0x00 0xff>;
 990                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
 991                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
 992                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
 993                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
 994                         clock-names = "pl_250m", "tl_26m", "peri_26m",
 995                                       "top_133m";
 996                         pinctrl-names = "default";
 997                         pinctrl-0 = <&pcie3_pins>;
 998                         #interrupt-cells = <1>;
 999                         interrupt-map-mask = <0 0 0 0x7>;
1000                         interrupt-map = <0 0 0 1 &pcie_intc3 0>,
1001                                         <0 0 0 2 &pcie_intc3 1>,
1002                                         <0 0 0 3 &pcie_intc3 2>,
1003                                         <0 0 0 4 &pcie_intc3 3>;
1004                         #address-cells = <3>;
1005                         #size-cells = <2>;
1006                         status = "disabled";
1007
1008                         pcie_intc3: interrupt-controller {
1009                                 #address-cells = <0>;
1010                                 #interrupt-cells = <1>;
1011                                 interrupt-controller;
1012                         };
1013                 };
1014
1015                 pcie0: pcie@11300000 {
1016                         compatible = "mediatek,mt7988-pcie",
1017                                      "mediatek,mt7986-pcie",
1018                                      "mediatek,mt8192-pcie";
1019                         reg = <0 0x11300000 0 0x2000>;
1020                         reg-names = "pcie-mac";
1021                         ranges = <0x81000000 0x00 0x30000000 0x00
1022                                   0x30000000 0x00 0x00200000>,
1023                                  <0x82000000 0x00 0x30200000 0x00
1024                                   0x30200000 0x00 0x07e00000>;
1025                         device_type = "pci";
1026                         linux,pci-domain = <0>;
1027                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1028                         bus-range = <0x00 0xff>;
1029                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
1030                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
1031                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
1032                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
1033                         clock-names = "pl_250m", "tl_26m", "peri_26m",
1034                                       "top_133m";
1035                         pinctrl-names = "default";
1036                         pinctrl-0 = <&pcie0_pins>;
1037                         #interrupt-cells = <1>;
1038                         interrupt-map-mask = <0 0 0 0x7>;
1039                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1040                                         <0 0 0 2 &pcie_intc0 1>,
1041                                         <0 0 0 3 &pcie_intc0 2>,
1042                                         <0 0 0 4 &pcie_intc0 3>;
1043                         #address-cells = <3>;
1044                         #size-cells = <2>;
1045                         status = "disabled";
1046
1047                         pcie_intc0: interrupt-controller {
1048                                 #address-cells = <0>;
1049                                 #interrupt-cells = <1>;
1050                                 interrupt-controller;
1051                         };
1052                 };
1053
1054                 pcie1: pcie@11310000 {
1055                         compatible = "mediatek,mt7988-pcie",
1056                                      "mediatek,mt7986-pcie",
1057                                      "mediatek,mt8192-pcie";
1058                         reg = <0 0x11310000 0 0x2000>;
1059                         reg-names = "pcie-mac";
1060                         ranges = <0x81000000 0x00 0x38000000 0x00
1061                                   0x38000000 0x00 0x00200000>,
1062                                  <0x82000000 0x00 0x38200000 0x00
1063                                   0x38200000 0x00 0x07e00000>;
1064                         device_type = "pci";
1065                         linux,pci-domain = <1>;
1066                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1067                         bus-range = <0x00 0xff>;
1068                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
1069                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
1070                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
1071                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
1072                         clock-names = "pl_250m", "tl_26m", "peri_26m",
1073                                       "top_133m";
1074                         pinctrl-names = "default";
1075                         pinctrl-0 = <&pcie1_pins>;
1076                         #interrupt-cells = <1>;
1077                         interrupt-map-mask = <0 0 0 0x7>;
1078                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1079                                         <0 0 0 2 &pcie_intc1 1>,
1080                                         <0 0 0 3 &pcie_intc1 2>,
1081                                         <0 0 0 4 &pcie_intc1 3>;
1082                         #address-cells = <3>;
1083                         #size-cells = <2>;
1084                         status = "disabled";
1085
1086                         pcie_intc1: interrupt-controller {
1087                                 #address-cells = <0>;
1088                                 #interrupt-cells = <1>;
1089                                 interrupt-controller;
1090                         };
1091                 };
1092
1093                 tphy: tphy@11c50000 {
1094                         compatible = "mediatek,mt7988",
1095                                      "mediatek,generic-tphy-v2";
1096                         ranges;
1097                         #address-cells = <2>;
1098                         #size-cells = <2>;
1099                         status = "disabled";
1100
1101                         tphyu2port0: usb-phy@11c50000 {
1102                                 reg = <0 0x11c50000 0 0x700>;
1103                                 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
1104                                 clock-names = "ref";
1105                                 #phy-cells = <1>;
1106                         };
1107
1108                         tphyu3port0: usb-phy@11c50700 {
1109                                 reg = <0 0x11c50700 0 0x900>;
1110                                 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
1111                                 clock-names = "ref";
1112                                 #phy-cells = <1>;
1113                                 mediatek,usb3-pll-ssc-delta;
1114                                 mediatek,usb3-pll-ssc-delta1;
1115                         };
1116                 };
1117
1118                 topmisc: topmisc@11d10000 {
1119                         compatible = "mediatek,mt7988-topmisc", "syscon",
1120                                      "mediatek,mt7988-power-controller";
1121                         reg = <0 0x11d10000 0 0x10000>;
1122                         #clock-cells = <1>;
1123                         #power-domain-cells = <1>;
1124                         #address-cells = <1>;
1125                         #size-cells = <0>;
1126                 };
1127
1128                 xphy: xphy@11e10000 {
1129                         compatible = "mediatek,mt7988",
1130                                      "mediatek,xsphy";
1131                         ranges;
1132                         #address-cells = <2>;
1133                         #size-cells = <2>;
1134                         status = "disabled";
1135
1136                         xphyu2port0: usb-phy@11e10000 {
1137                                 reg = <0 0x11e10000 0 0x400>;
1138                                 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1139                                 clock-names = "ref";
1140                                 #phy-cells = <1>;
1141                         };
1142
1143                         xphyu3port0: usb-phy@11e13000 {
1144                                 reg = <0 0x11e13400 0 0x500>;
1145                                 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1146                                 clock-names = "ref";
1147                                 #phy-cells = <1>;
1148                                 mediatek,syscon-type = <&topmisc 0x218 0>;
1149                         };
1150                 };
1151
1152                 xfi_tphy0: phy@11f20000 {
1153                         compatible = "mediatek,mt7988-xfi-tphy";
1154                         reg = <0 0x11f20000 0 0x10000>;
1155                         resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
1156                         clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
1157                         clock-names = "xfipll", "topxtal";
1158                         mediatek,usxgmii-performance-errata;
1159                         #phy-cells = <0>;
1160                 };
1161
1162                 xfi_tphy1: phy@11f30000 {
1163                         compatible = "mediatek,mt7988-xfi-tphy";
1164                         reg = <0 0x11f30000 0 0x10000>;
1165                         resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
1166                         clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
1167                         clock-names = "xfipll", "topxtal";
1168                         #phy-cells = <0>;
1169                 };
1170
1171                 xfi_pll: clock-controller@11f40000 {
1172                         compatible = "mediatek,mt7988-xfi-pll";
1173                         reg = <0 0x11f40000 0 0x1000>;
1174                         resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
1175                         #clock-cells = <1>;
1176                 };
1177
1178                 efuse: efuse@11f50000 {
1179                         compatible = "mediatek,efuse";
1180                         reg = <0 0x11f50000 0 0x1000>;
1181                         #address-cells = <1>;
1182                         #size-cells = <1>;
1183
1184                         lvts_calibration: calib@918 {
1185                                 reg = <0x918 0x28>;
1186                         };
1187
1188                         phy_calibration_p0: calib@940 {
1189                                 reg = <0x940 0x10>;
1190                         };
1191
1192                         phy_calibration_p1: calib@954 {
1193                                 reg = <0x954 0x10>;
1194                         };
1195
1196                         phy_calibration_p2: calib@968 {
1197                                 reg = <0x968 0x10>;
1198                         };
1199
1200                         phy_calibration_p3: calib@97c {
1201                                 reg = <0x97c 0x10>;
1202                         };
1203
1204                         cpufreq_calibration: calib@278 {
1205                                 reg = <0x278 0x1>;
1206                         };
1207                 };
1208
1209                 ethsys: syscon@15000000 {
1210                         compatible = "mediatek,mt7988-ethsys", "syscon";
1211                         reg = <0 0x15000000 0 0x1000>;
1212                         #clock-cells = <1>;
1213                         #reset-cells = <1>;
1214                         #address-cells = <1>;
1215                         #size-cells = <1>;
1216                 };
1217
1218                 switch: switch@15020000 {
1219                         compatible = "mediatek,mt7988-switch";
1220                         reg = <0 0x15020000 0 0x8000>;
1221                         interrupt-controller;
1222                         #interrupt-cells = <1>;
1223                         interrupt-parent = <&gic>;
1224                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1225                         resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
1226                         #address-cells = <1>;
1227                         #size-cells = <1>;
1228
1229                         ports {
1230                                 #address-cells = <1>;
1231                                 #size-cells = <0>;
1232
1233                                 port@0 {
1234                                         reg = <0>;
1235                                         label = "lan0";
1236                                         phy-mode = "internal";
1237                                         phy-handle = <&gsw_phy0>;
1238                                 };
1239
1240                                 port@1 {
1241                                         reg = <1>;
1242                                         label = "lan1";
1243                                         phy-mode = "internal";
1244                                         phy-handle = <&gsw_phy1>;
1245                                 };
1246
1247                                 port@2 {
1248                                         reg = <2>;
1249                                         label = "lan2";
1250                                         phy-mode = "internal";
1251                                         phy-handle = <&gsw_phy2>;
1252                                 };
1253
1254                                 port@3 {
1255                                         reg = <3>;
1256                                         label = "lan3";
1257                                         phy-mode = "internal";
1258                                         phy-handle = <&gsw_phy3>;
1259                                 };
1260
1261                                 port@6 {
1262                                         reg = <6>;
1263                                         ethernet = <&gmac0>;
1264                                         phy-mode = "internal";
1265
1266                                         fixed-link {
1267                                                 speed = <10000>;
1268                                                 full-duplex;
1269                                                 pause;
1270                                         };
1271                                 };
1272                         };
1273
1274                         mdio {
1275                                 #address-cells = <1>;
1276                                 #size-cells = <0>;
1277                                 mediatek,pio = <&pio>;
1278
1279                                 gsw_phy0: ethernet-phy@0 {
1280                                         compatible = "ethernet-phy-ieee802.3-c22";
1281                                         reg = <0>;
1282                                         phy-mode = "internal";
1283                                         nvmem-cells = <&phy_calibration_p0>;
1284                                         nvmem-cell-names = "phy-cal-data";
1285
1286                                         leds {
1287                                                 #address-cells = <1>;
1288                                                 #size-cells = <0>;
1289
1290                                                 gsw_phy0_led0: gsw-phy0-led0@0 {
1291                                                         reg = <0>;
1292                                                         function = LED_FUNCTION_LAN;
1293                                                         status = "disabled";
1294                                                 };
1295
1296                                                 gsw_phy0_led1: gsw-phy0-led1@1 {
1297                                                         reg = <1>;
1298                                                         function = LED_FUNCTION_LAN;
1299                                                         status = "disabled";
1300                                                 };
1301                                         };
1302                                 };
1303
1304                                 gsw_phy1: ethernet-phy@1 {
1305                                         compatible = "ethernet-phy-ieee802.3-c22";
1306                                         reg = <1>;
1307                                         phy-mode = "internal";
1308                                         nvmem-cells = <&phy_calibration_p1>;
1309                                         nvmem-cell-names = "phy-cal-data";
1310
1311                                         leds {
1312                                                 #address-cells = <1>;
1313                                                 #size-cells = <0>;
1314
1315                                                 gsw_phy1_led0: gsw-phy1-led0@0 {
1316                                                         reg = <0>;
1317                                                         function = LED_FUNCTION_LAN;
1318                                                         status = "disabled";
1319                                                 };
1320
1321                                                 gsw_phy1_led1: gsw-phy1-led1@1 {
1322                                                         reg = <1>;
1323                                                         function = LED_FUNCTION_LAN;
1324                                                         status = "disabled";
1325                                                 };
1326                                         };
1327                                 };
1328
1329                                 gsw_phy2: ethernet-phy@2 {
1330                                         compatible = "ethernet-phy-ieee802.3-c22";
1331                                         reg = <2>;
1332                                         phy-mode = "internal";
1333                                         nvmem-cells = <&phy_calibration_p2>;
1334                                         nvmem-cell-names = "phy-cal-data";
1335
1336                                         leds {
1337                                                 #address-cells = <1>;
1338                                                 #size-cells = <0>;
1339
1340                                                 gsw_phy2_led0: gsw-phy2-led0@0 {
1341                                                         reg = <0>;
1342                                                         function = LED_FUNCTION_LAN;
1343                                                         status = "disabled";
1344                                                 };
1345
1346                                                 gsw_phy2_led1: gsw-phy2-led1@1 {
1347                                                         reg = <1>;
1348                                                         function = LED_FUNCTION_LAN;
1349                                                         status = "disabled";
1350                                                 };
1351                                         };
1352                                 };
1353
1354                                 gsw_phy3: ethernet-phy@3 {
1355                                         compatible = "ethernet-phy-ieee802.3-c22";
1356                                         reg = <3>;
1357                                         phy-mode = "internal";
1358                                         nvmem-cells = <&phy_calibration_p3>;
1359                                         nvmem-cell-names = "phy-cal-data";
1360
1361                                         leds {
1362                                                 #address-cells = <1>;
1363                                                 #size-cells = <0>;
1364
1365                                                 gsw_phy3_led0: gsw-phy3-led0@0 {
1366                                                         reg = <0>;
1367                                                         function = LED_FUNCTION_LAN;
1368                                                         status = "disabled";
1369                                                 };
1370
1371                                                 gsw_phy3_led1: gsw-phy3-led1@1 {
1372                                                         reg = <1>;
1373                                                         function = LED_FUNCTION_LAN;
1374                                                         status = "disabled";
1375                                                 };
1376                                         };
1377                                 };
1378                         };
1379                 };
1380
1381                 ethwarp: clock-controller@15031000 {
1382                         compatible = "mediatek,mt7988-ethwarp";
1383                         reg = <0 0x15031000 0 0x1000>;
1384                         #clock-cells = <1>;
1385                         #reset-cells = <1>;
1386                 };
1387
1388                 eth: ethernet@15100000 {
1389                         compatible = "mediatek,mt7988-eth";
1390                         reg = <0 0x15100000 0 0x80000>,
1391                               <0 0x15400000 0 0x380000>;
1392                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1393                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1394                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1395                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1396                         clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1397                                  <&ethsys CLK_ETHDMA_XGP2_EN>,
1398                                  <&ethsys CLK_ETHDMA_XGP3_EN>,
1399                                  <&ethsys CLK_ETHDMA_FE_EN>,
1400                                  <&ethsys CLK_ETHDMA_GP2_EN>,
1401                                  <&ethsys CLK_ETHDMA_GP1_EN>,
1402                                  <&ethsys CLK_ETHDMA_GP3_EN>,
1403                                  <&ethsys CLK_ETHDMA_ESW_EN>,
1404                                  <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1405                                  <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1406                                  <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1407                                  <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1408                                  <&topckgen CLK_TOP_ETH_GMII_SEL>,
1409                                  <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1410                                  <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1411                                  <&topckgen CLK_TOP_ETH_SYS_SEL>,
1412                                  <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1413                                  <&topckgen CLK_TOP_ETH_MII_SEL>,
1414                                  <&topckgen CLK_TOP_NETSYS_SEL>,
1415                                  <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1416                                  <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1417                                  <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1418                                  <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1419                                  <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1420                         clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1421                                       "gp3", "esw", "crypto",
1422                                       "ethwarp_wocpu2", "ethwarp_wocpu1",
1423                                       "ethwarp_wocpu0", "top_eth_gmii_sel",
1424                                       "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1425                                       "top_eth_sys_sel", "top_eth_xgmii_sel",
1426                                       "top_eth_mii_sel", "top_netsys_sel",
1427                                       "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1428                                       "top_netsys_sync_250m_sel",
1429                                       "top_netsys_ppefb_250m_sel",
1430                                       "top_netsys_warp_sel";
1431                         assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1432                                           <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1433                                           <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1434                                           <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1435                                           <&topckgen CLK_TOP_SGM_0_SEL>,
1436                                           <&topckgen CLK_TOP_SGM_1_SEL>;
1437                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1438                                                  <&topckgen CLK_TOP_NET1PLL_D4>,
1439                                                  <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1440                                                  <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1441                                                  <&apmixedsys CLK_APMIXED_SGMPLL>,
1442                                                  <&apmixedsys CLK_APMIXED_SGMPLL>;
1443                         mediatek,ethsys = <&ethsys>;
1444                         mediatek,infracfg = <&topmisc>;
1445                         #address-cells = <1>;
1446                         #size-cells = <0>;
1447
1448                         gmac0: mac@0 {
1449                                 compatible = "mediatek,eth-mac";
1450                                 reg = <0>;
1451                                 phy-mode = "internal";
1452                                 status = "disabled";
1453
1454                                 fixed-link {
1455                                         speed = <10000>;
1456                                         full-duplex;
1457                                         pause;
1458                                 };
1459                         };
1460
1461                         gmac1: mac@1 {
1462                                 compatible = "mediatek,eth-mac";
1463                                 reg = <1>;
1464                                 status = "disabled";
1465                                 pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
1466                                 phys = <&xfi_tphy1>;
1467                         };
1468
1469                         gmac2: mac@2 {
1470                                 compatible = "mediatek,eth-mac";
1471                                 reg = <2>;
1472                                 status = "disabled";
1473                                 pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
1474                                 phys = <&xfi_tphy0>;
1475                         };
1476
1477                         mdio_bus: mdio-bus {
1478                                 #address-cells = <1>;
1479                                 #size-cells = <0>;
1480
1481                                 /* internal 2.5G PHY */
1482                                 int_2p5g_phy: ethernet-phy@15 {
1483                                         compatible = "ethernet-phy-ieee802.3-c45";
1484                                         reg = <15>;
1485                                         phy-mode = "internal";
1486                                 };
1487                         };
1488                 };
1489
1490                 crypto: crypto@15600000 {
1491                         compatible = "inside-secure,safexcel-eip197b";
1492                         reg = <0 0x15600000 0 0x180000>;
1493                         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1494                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1495                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1496                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1497                         interrupt-names = "ring0", "ring1", "ring2", "ring3";
1498                         status = "okay";
1499                 };
1500         };
1501
1502         thermal-zones {
1503                 cpu_thermal: cpu-thermal {
1504                         polling-delay-passive = <1000>;
1505                         polling-delay = <1000>;
1506                         thermal-sensors = <&lvts 0>;
1507
1508                         trips {
1509                                 cpu_trip_crit: crit {
1510                                         temperature = <125000>;
1511                                         hysteresis = <2000>;
1512                                         type = "critical";
1513                                 };
1514
1515                                 cpu_trip_hot: hot {
1516                                         temperature = <120000>;
1517                                         hysteresis = <2000>;
1518                                         type = "hot";
1519                                 };
1520
1521                                 cpu_trip_active_high: active-high {
1522                                         temperature = <115000>;
1523                                         hysteresis = <2000>;
1524                                         type = "active";
1525                                 };
1526
1527                                 cpu_trip_active_med: active-med {
1528                                         temperature = <85000>;
1529                                         hysteresis = <2000>;
1530                                         type = "active";
1531                                 };
1532
1533                                 cpu_trip_active_low: active-low {
1534                                         temperature = <40000>;
1535                                         hysteresis = <2000>;
1536                                         type = "active";
1537                                 };
1538                         };
1539
1540                         cooling-maps {
1541                                 cpu-active-high {
1542                                 /* active: set fan to cooling level 2 */
1543                                         cooling-device = <&fan 3 3>;
1544                                         trip = <&cpu_trip_active_high>;
1545                                 };
1546
1547                                 cpu-active-low {
1548                                 /* active: set fan to cooling level 1 */
1549                                         cooling-device = <&fan 2 2>;
1550                                         trip = <&cpu_trip_active_med>;
1551                                 };
1552
1553                                 cpu-passive {
1554                                 /* passive: set fan to cooling level 0 */
1555                                         cooling-device = <&fan 1 1>;
1556                                         trip = <&cpu_trip_active_low>;
1557                                 };
1558                         };
1559                 };
1560         };
1561
1562         timer {
1563                 compatible = "arm,armv8-timer";
1564                 interrupt-parent = <&gic>;
1565                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1566                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1567                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1568                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1569         };
1570 };