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mediatek: filogic: update MT7988 device tree
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/ti-syscon.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 compatible = "mediatek,mt7988";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 clk40m: oscillator@0 {
23 compatible = "fixed-clock";
24 clock-frequency = <40000000>;
25 #clock-cells = <0>;
26 clock-output-names = "clkxtal";
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32 cpu0: cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a73";
35 enable-method = "psci";
36 reg = <0x0>;
37 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
38 <&topckgen CLK_TOP_XTAL>;
39 clock-names = "cpu", "intermediate";
40 operating-points-v2 = <&cluster0_opp>;
41 mediatek,cci = <&cci>;
42 };
43
44 cpu1: cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a73";
47 enable-method = "psci";
48 reg = <0x1>;
49 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
50 <&topckgen CLK_TOP_XTAL>;
51 clock-names = "cpu", "intermediate";
52 operating-points-v2 = <&cluster0_opp>;
53 mediatek,cci = <&cci>;
54 };
55
56 cpu2: cpu@2 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a73";
59 enable-method = "psci";
60 reg = <0x2>;
61 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
62 <&topckgen CLK_TOP_XTAL>;
63 clock-names = "cpu", "intermediate";
64 operating-points-v2 = <&cluster0_opp>;
65 mediatek,cci = <&cci>;
66 };
67
68 cpu3: cpu@3 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a73";
71 enable-method = "psci";
72 reg = <0x3>;
73 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
74 <&topckgen CLK_TOP_XTAL>;
75 clock-names = "cpu", "intermediate";
76 operating-points-v2 = <&cluster0_opp>;
77 mediatek,cci = <&cci>;
78 };
79
80 cluster0_opp: opp_table0 {
81 compatible = "operating-points-v2";
82 opp-shared;
83 opp00 {
84 opp-hz = /bits/ 64 <800000000>;
85 opp-microvolt = <850000>;
86 };
87 opp01 {
88 opp-hz = /bits/ 64 <1100000000>;
89 opp-microvolt = <850000>;
90 };
91 opp02 {
92 opp-hz = /bits/ 64 <1500000000>;
93 opp-microvolt = <850000>;
94 };
95 opp03 {
96 opp-hz = /bits/ 64 <1800000000>;
97 opp-microvolt = <900000>;
98 };
99 };
100 };
101
102 cci: cci {
103 compatible = "mediatek,mt7988-cci",
104 "mediatek,mt8183-cci";
105 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
106 <&topckgen CLK_TOP_XTAL>;
107 clock-names = "cci", "intermediate";
108 operating-points-v2 = <&cci_opp>;
109 };
110
111 cci_opp: opp_table_cci {
112 compatible = "operating-points-v2";
113 opp-shared;
114 opp00 {
115 opp-hz = /bits/ 64 <480000000>;
116 opp-microvolt = <850000>;
117 };
118 opp01 {
119 opp-hz = /bits/ 64 <660000000>;
120 opp-microvolt = <850000>;
121 };
122 opp02 {
123 opp-hz = /bits/ 64 <900000000>;
124 opp-microvolt = <850000>;
125 };
126 opp03 {
127 opp-hz = /bits/ 64 <1080000000>;
128 opp-microvolt = <900000>;
129 };
130 };
131
132 pmu {
133 compatible = "arm,cortex-a73-pmu";
134 interrupt-parent = <&gic>;
135 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
136 };
137
138 psci {
139 compatible = "arm,psci-0.2";
140 method = "smc";
141 };
142
143 reserved-memory {
144 #address-cells = <2>;
145 #size-cells = <2>;
146 ranges;
147
148 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
149 secmon_reserved: secmon@43000000 {
150 reg = <0 0x43000000 0 0x50000>;
151 no-map;
152 };
153 };
154
155 timer {
156 compatible = "arm,armv8-timer";
157 interrupt-parent = <&gic>;
158 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
159 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
160 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
161 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
162 };
163
164 soc {
165 #address-cells = <2>;
166 #size-cells = <2>;
167 compatible = "simple-bus";
168 ranges;
169
170 gic: interrupt-controller@c000000 {
171 compatible = "arm,gic-v3";
172 #interrupt-cells = <3>;
173 interrupt-parent = <&gic>;
174 interrupt-controller;
175 reg = <0 0x0c000000 0 0x40000>, /* GICD */
176 <0 0x0c080000 0 0x200000>, /* GICR */
177 <0 0x0c400000 0 0x2000>, /* GICC */
178 <0 0x0c410000 0 0x1000>, /* GICH */
179 <0 0x0c420000 0 0x2000>; /* GICV */
180
181 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
182 };
183
184 phyfw: phy-firmware@f000000 {
185 compatible = "mediatek,2p5gphy-fw";
186 reg = <0 0x0f000000 0 0x8000>,
187 <0 0x0f100000 0 0x20000>,
188 <0 0x0f0f0000 0 0x200>;
189 };
190
191 infracfg: infracfg@10001000 {
192 compatible = "mediatek,mt7988-infracfg", "syscon";
193 reg = <0 0x10001000 0 0x1000>;
194 #clock-cells = <1>;
195 };
196
197 topckgen: topckgen@1001b000 {
198 compatible = "mediatek,mt7988-topckgen", "syscon";
199 reg = <0 0x1001b000 0 0x1000>;
200 #clock-cells = <1>;
201 };
202
203 watchdog: watchdog@1001c000 {
204 compatible = "mediatek,mt7988-wdt",
205 "mediatek,mt6589-wdt",
206 "syscon";
207 reg = <0 0x1001c000 0 0x1000>;
208 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
209 #reset-cells = <1>;
210 };
211
212 apmixedsys: apmixedsys@1001e000 {
213 compatible = "mediatek,mt7988-apmixedsys";
214 reg = <0 0x1001e000 0 0x1000>;
215 #clock-cells = <1>;
216 };
217
218 pio: pinctrl@1001f000 {
219 compatible = "mediatek,mt7988-pinctrl", "syscon";
220 reg = <0 0x1001f000 0 0x1000>,
221 <0 0x11c10000 0 0x1000>,
222 <0 0x11d00000 0 0x1000>,
223 <0 0x11d20000 0 0x1000>,
224 <0 0x11e00000 0 0x1000>,
225 <0 0x11f00000 0 0x1000>,
226 <0 0x1000b000 0 0x1000>;
227 reg-names = "gpio_base", "iocfg_tr_base",
228 "iocfg_br_base", "iocfg_rb_base",
229 "iocfg_lb_base", "iocfg_tl_base", "eint";
230 gpio-controller;
231 #gpio-cells = <2>;
232 gpio-ranges = <&pio 0 0 84>;
233 interrupt-controller;
234 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-parent = <&gic>;
236 #interrupt-cells = <2>;
237
238 mdio0_pins: mdio0-pins {
239 mux {
240 function = "eth";
241 groups = "mdc_mdio0";
242 };
243
244 conf {
245 groups = "mdc_mdio0";
246 drive-strength = <MTK_DRIVE_8mA>;
247 };
248 };
249
250 i2c0_pins: i2c0-pins-g0 {
251 mux {
252 function = "i2c";
253 groups = "i2c0_1";
254 };
255 };
256
257 i2c1_pins: i2c1-pins-g0 {
258 mux {
259 function = "i2c";
260 groups = "i2c1_0";
261 };
262 };
263
264 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
265 mux {
266 function = "i2c";
267 groups = "i2c1_sfp";
268 };
269 };
270
271 i2c2_pins: i2c2-pins {
272 mux {
273 function = "i2c";
274 groups = "i2c2";
275 };
276 };
277
278 i2c2_0_pins: i2c2-pins-g0 {
279 mux {
280 function = "i2c";
281 groups = "i2c2_0";
282 };
283 };
284
285 i2c2_1_pins: i2c2-pins-g1 {
286 mux {
287 function = "i2c";
288 groups = "i2c2_1";
289 };
290 };
291
292 gbe0_led0_pins: gbe0-led0-pins {
293 mux {
294 function = "led";
295 groups = "gbe0_led0";
296 };
297 };
298
299 gbe1_led0_pins: gbe1-led0-pins {
300 mux {
301 function = "led";
302 groups = "gbe1_led0";
303 };
304 };
305
306 gbe2_led0_pins: gbe2-led0-pins {
307 mux {
308 function = "led";
309 groups = "gbe2_led0";
310 };
311 };
312
313 gbe3_led0_pins: gbe3-led0-pins {
314 mux {
315 function = "led";
316 groups = "gbe3_led0";
317 };
318 };
319
320 gbe0_led1_pins: gbe0-led1-pins {
321 mux {
322 function = "led";
323 groups = "gbe0_led1";
324 };
325 };
326
327 gbe1_led1_pins: gbe1-led1-pins {
328 mux {
329 function = "led";
330 groups = "gbe1_led1";
331 };
332 };
333
334 gbe2_led1_pins: gbe2-led1-pins {
335 mux {
336 function = "led";
337 groups = "gbe2_led1";
338 };
339 };
340
341 gbe3_led1_pins: gbe3-led1-pins {
342 mux {
343 function = "led";
344 groups = "gbe3_led1";
345 };
346 };
347
348 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
349 mux {
350 function = "led";
351 groups = "2p5gbe_led0";
352 };
353 };
354
355 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
356 mux {
357 function = "led";
358 groups = "2p5gbe_led1";
359 };
360 };
361
362 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
363 mux {
364 function = "flash";
365 groups = "emmc_45";
366 };
367 };
368
369 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
370 mux {
371 function = "flash";
372 groups = "emmc_51";
373 };
374 };
375
376 mmc0_pins_sdcard: mmc0-pins-sdcard {
377 mux {
378 function = "flash";
379 groups = "sdcard";
380 };
381 };
382
383 uart0_pins: uart0-pins {
384 mux {
385 function = "uart";
386 groups = "uart0";
387 };
388 };
389 };
390
391 sgmiisys0: syscon@10060000 {
392 compatible = "mediatek,mt7988-sgmiisys",
393 "mediatek,mt7988-sgmiisys_0",
394 "syscon";
395 reg = <0 0x10060000 0 0x1000>;
396 #clock-cells = <1>;
397 };
398
399 sgmiisys1: syscon@10070000 {
400 compatible = "mediatek,mt7988-sgmiisys",
401 "mediatek,mt7988-sgmiisys_1",
402 "syscon";
403 reg = <0 0x10070000 0 0x1000>;
404 #clock-cells = <1>;
405 };
406
407 usxgmiisys0: usxgmiisys@10080000 {
408 compatible = "mediatek,mt7988-usxgmiisys",
409 "mediatek,mt7988-usxgmiisys_0",
410 "syscon";
411 reg = <0 0x10080000 0 0x1000>;
412 #clock-cells = <1>;
413 };
414
415 usxgmiisys1: usxgmiisys@10081000 {
416 compatible = "mediatek,mt7988-usxgmiisys",
417 "mediatek,mt7988-usxgmiisys_1",
418 "syscon";
419 reg = <0 0x10081000 0 0x1000>;
420 #clock-cells = <1>;
421 };
422
423 xfi_pextp0: xfi_pextp@11f20000 {
424 compatible = "mediatek,mt7988-xfi_pextp",
425 "mediatek,mt7988-xfi_pextp_0",
426 "syscon";
427 reg = <0 0x11f20000 0 0x10000>;
428 #clock-cells = <1>;
429 };
430
431 xfi_pextp1: xfi_pextp@11f30000 {
432 compatible = "mediatek,mt7988-xfi_pextp",
433 "mediatek,mt7988-xfi_pextp_1",
434 "syscon";
435 reg = <0 0x11f30000 0 0x10000>;
436 #clock-cells = <1>;
437 };
438
439 xfi_pll: xfi_pll@11f40000 {
440 compatible = "mediatek,mt7988-xfi_pll", "syscon";
441 reg = <0 0x11f40000 0 0x1000>;
442 #clock-cells = <1>;
443 };
444
445 mcusys: mcusys@100e0000 {
446 compatible = "mediatek,mt7988-mcusys", "syscon";
447 reg = <0 0x100e0000 0 0x1000>;
448 #clock-cells = <1>;
449 };
450
451 uart0: serial@11000000 {
452 compatible = "mediatek,mt7986-uart",
453 "mediatek,mt6577-uart";
454 reg = <0 0x11000000 0 0x100>;
455 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
456 /*
457 * 8250-mtk driver don't control "baud" clock since commit
458 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
459 * still need to be passed to the driver to prevent probe fail
460 */
461 clocks = <&topckgen CLK_TOP_UART_SEL>,
462 <&infracfg CLK_INFRA_52M_UART0_CK>;
463 clock-names = "baud", "bus";
464 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
465 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
466 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
467 <&topckgen CLK_TOP_UART_SEL>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&uart0_pins>;
470 status = "disabled";
471 };
472
473 i2c0: i2c@11003000 {
474 compatible = "mediatek,mt7988-i2c",
475 "mediatek,mt7981-i2c";
476 reg = <0 0x11003000 0 0x1000>,
477 <0 0x10217080 0 0x80>;
478 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
479 clock-div = <1>;
480 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
481 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
482 clock-names = "main", "dma";
483 #address-cells = <1>;
484 #size-cells = <0>;
485 status = "disabled";
486 };
487
488 i2c1: i2c@11004000 {
489 compatible = "mediatek,mt7988-i2c",
490 "mediatek,mt7981-i2c";
491 reg = <0 0x11004000 0 0x1000>,
492 <0 0x10217100 0 0x80>;
493 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
494 clock-div = <1>;
495 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
496 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
497 clock-names = "main", "dma";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 status = "disabled";
501 };
502
503 i2c2: i2c@11005000 {
504 compatible = "mediatek,mt7988-i2c",
505 "mediatek,mt7981-i2c";
506 reg = <0 0x11005000 0 0x1000>,
507 <0 0x10217180 0 0x80>;
508 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
509 clock-div = <1>;
510 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
511 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
512 clock-names = "main", "dma";
513 #address-cells = <1>;
514 #size-cells = <0>;
515 status = "disabled";
516 };
517
518 spi0: spi@11007000 {
519 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
520 reg = <0 0x11007000 0 0x100>;
521 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&topckgen CLK_TOP_MPLL_D2>,
523 <&topckgen CLK_TOP_SPI_SEL>,
524 <&infracfg CLK_INFRA_104M_SPI0>,
525 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
526 clock-names = "parent-clk", "sel-clk", "spi-clk",
527 "spi-hclk";
528
529 #address-cells = <1>;
530 #size-cells = <0>;
531
532 status = "disabled";
533 };
534
535 pcie2: pcie@11280000 {
536 compatible = "mediatek,mt7988-pcie",
537 "mediatek,mt7986-pcie",
538 "mediatek,mt8192-pcie";
539 device_type = "pci";
540 #address-cells = <3>;
541 #size-cells = <2>;
542 reg = <0 0x11280000 0 0x2000>;
543 reg-names = "pcie-mac";
544 linux,pci-domain = <3>;
545 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
546 bus-range = <0x00 0xff>;
547 ranges = <0x81000000 0x00 0x20000000 0x00
548 0x20000000 0x00 0x00200000>,
549 <0x82000000 0x00 0x20200000 0x00
550 0x20200000 0x00 0x07e00000>;
551 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
552 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
553 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
554 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
555 clock-names = "pl_250m", "tl_26m", "peri_26m",
556 "top_133m";
557 status = "disabled";
558
559 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
560 phy-names = "pcie-phy";
561
562 #interrupt-cells = <1>;
563 interrupt-map-mask = <0 0 0 0x7>;
564 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
565 <0 0 0 2 &pcie_intc2 1>,
566 <0 0 0 3 &pcie_intc2 2>,
567 <0 0 0 4 &pcie_intc2 3>;
568 pcie_intc2: interrupt-controller {
569 #address-cells = <0>;
570 #interrupt-cells = <1>;
571 interrupt-controller;
572 };
573 };
574
575 pcie3: pcie@11290000 {
576 compatible = "mediatek,mt7988-pcie",
577 "mediatek,mt7986-pcie",
578 "mediatek,mt8192-pcie";
579 device_type = "pci";
580 #address-cells = <3>;
581 #size-cells = <2>;
582 reg = <0 0x11290000 0 0x2000>;
583 reg-names = "pcie-mac";
584 linux,pci-domain = <2>;
585 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
586 bus-range = <0x00 0xff>;
587 ranges = <0x81000000 0x00 0x28000000 0x00
588 0x28000000 0x00 0x00200000>,
589 <0x82000000 0x00 0x28200000 0x00
590 0x28200000 0x00 0x07e00000>;
591 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
592 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
593 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
594 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
595 clock-names = "pl_250m", "tl_26m", "peri_26m",
596 "top_133m";
597 status = "disabled";
598
599 #interrupt-cells = <1>;
600 interrupt-map-mask = <0 0 0 0x7>;
601 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
602 <0 0 0 2 &pcie_intc3 1>,
603 <0 0 0 3 &pcie_intc3 2>,
604 <0 0 0 4 &pcie_intc3 3>;
605 pcie_intc3: interrupt-controller {
606 #address-cells = <0>;
607 #interrupt-cells = <1>;
608 interrupt-controller;
609 };
610 };
611
612 pcie0: pcie@11300000 {
613 compatible = "mediatek,mt7988-pcie",
614 "mediatek,mt7986-pcie",
615 "mediatek,mt8192-pcie";
616 device_type = "pci";
617 #address-cells = <3>;
618 #size-cells = <2>;
619 reg = <0 0x11300000 0 0x2000>;
620 reg-names = "pcie-mac";
621 linux,pci-domain = <0>;
622 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
623 bus-range = <0x00 0xff>;
624 ranges = <0x81000000 0x00 0x30000000 0x00
625 0x30000000 0x00 0x00200000>,
626 <0x82000000 0x00 0x30200000 0x00
627 0x30200000 0x00 0x07e00000>;
628 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
629 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
630 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
631 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
632 clock-names = "pl_250m", "tl_26m", "peri_26m",
633 "top_133m";
634 status = "disabled";
635
636 #interrupt-cells = <1>;
637 interrupt-map-mask = <0 0 0 0x7>;
638 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
639 <0 0 0 2 &pcie_intc0 1>,
640 <0 0 0 3 &pcie_intc0 2>,
641 <0 0 0 4 &pcie_intc0 3>;
642 pcie_intc0: interrupt-controller {
643 #address-cells = <0>;
644 #interrupt-cells = <1>;
645 interrupt-controller;
646 };
647 };
648
649 pcie1: pcie@11310000 {
650 compatible = "mediatek,mt7988-pcie",
651 "mediatek,mt7986-pcie",
652 "mediatek,mt8192-pcie";
653 device_type = "pci";
654 #address-cells = <3>;
655 #size-cells = <2>;
656 reg = <0 0x11310000 0 0x2000>;
657 reg-names = "pcie-mac";
658 linux,pci-domain = <1>;
659 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
660 bus-range = <0x00 0xff>;
661 ranges = <0x81000000 0x00 0x38000000 0x00
662 0x38000000 0x00 0x00200000>,
663 <0x82000000 0x00 0x38200000 0x00
664 0x38200000 0x00 0x07e00000>;
665 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
666 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
667 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
668 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
669 clock-names = "pl_250m", "tl_26m", "peri_26m",
670 "top_133m";
671 status = "disabled";
672
673 #interrupt-cells = <1>;
674 interrupt-map-mask = <0 0 0 0x7>;
675 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
676 <0 0 0 2 &pcie_intc1 1>,
677 <0 0 0 3 &pcie_intc1 2>,
678 <0 0 0 4 &pcie_intc1 3>;
679 pcie_intc1: interrupt-controller {
680 #address-cells = <0>;
681 #interrupt-cells = <1>;
682 interrupt-controller;
683 };
684 };
685
686 ssusb0: usb@11190000 {
687 compatible = "mediatek,mt7988-xhci",
688 "mediatek,mtk-xhci";
689 reg = <0 0x11190000 0 0x2e00>,
690 <0 0x11193e00 0 0x0100>;
691 reg-names = "mac", "ippc";
692 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
693 phys = <&xphyu2port0 PHY_TYPE_USB2>,
694 <&xphyu3port0 PHY_TYPE_USB3>;
695 clocks = <&infracfg CLK_INFRA_USB_SYS>,
696 <&infracfg CLK_INFRA_USB_XHCI>,
697 <&infracfg CLK_INFRA_USB_REF>,
698 <&infracfg CLK_INFRA_66M_USB_HCK>,
699 <&infracfg CLK_INFRA_133M_USB_HCK>;
700 clock-names = "sys_ck",
701 "xhci_ck",
702 "ref_ck",
703 "mcu_ck",
704 "dma_ck";
705 #address-cells = <2>;
706 #size-cells = <2>;
707 mediatek,p0_speed_fixup;
708 status = "disabled";
709 };
710
711 ssusb1: usb@11200000 {
712 compatible = "mediatek,mt7988-xhci",
713 "mediatek,mtk-xhci";
714 reg = <0 0x11200000 0 0x2e00>,
715 <0 0x11203e00 0 0x0100>;
716 reg-names = "mac", "ippc";
717 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
718 phys = <&tphyu2port0 PHY_TYPE_USB2>,
719 <&tphyu3port0 PHY_TYPE_USB3>;
720 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
721 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
722 <&infracfg CLK_INFRA_USB_CK_P1>,
723 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
724 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
725 clock-names = "sys_ck",
726 "xhci_ck",
727 "ref_ck",
728 "mcu_ck",
729 "dma_ck";
730 #address-cells = <2>;
731 #size-cells = <2>;
732 status = "disabled";
733 };
734
735 mmc0: mmc@11230000 {
736 compatible = "mediatek,mt7986-mmc",
737 "mediatek,mt7981-mmc";
738 reg = <0 0x11230000 0 0x1000>,
739 <0 0x11D60000 0 0x1000>;
740 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&infracfg CLK_INFRA_MSDC400>,
742 <&infracfg CLK_INFRA_MSDC2_HCK>,
743 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
744 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
745 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
746 <&topckgen CLK_TOP_EMMC_400M_SEL>;
747 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
748 <&apmixedsys CLK_APMIXED_MSDCPLL>;
749 clock-names = "source",
750 "hclk",
751 "axi_cg",
752 "ahb_cg";
753 #address-cells = <1>;
754 #size-cells = <0>;
755 status = "disabled";
756 };
757
758 tphy: tphy@11c50000 {
759 compatible = "mediatek,mt7988",
760 "mediatek,generic-tphy-v2";
761 #address-cells = <2>;
762 #size-cells = <2>;
763 ranges;
764 status = "disabled";
765 tphyu2port0: usb-phy@11c50000 {
766 reg = <0 0x11c50000 0 0x700>;
767 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
768 clock-names = "ref";
769 #phy-cells = <1>;
770 };
771 tphyu3port0: usb-phy@11c50700 {
772 reg = <0 0x11c50700 0 0x900>;
773 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
774 clock-names = "ref";
775 #phy-cells = <1>;
776 mediatek,usb3-pll-ssc-delta;
777 mediatek,usb3-pll-ssc-delta1;
778 };
779 };
780
781 topmisc: topmisc@11d10000 {
782 compatible = "mediatek,mt7988-topmisc", "syscon",
783 "mediatek,mt7988-power-controller";
784 reg = <0 0x11d10000 0 0x10000>;
785 #clock-cells = <1>;
786 #power-domain-cells = <1>;
787 #address-cells = <1>;
788 #size-cells = <0>;
789 };
790
791 xphy: xphy@11e10000 {
792 compatible = "mediatek,mt7988",
793 "mediatek,xsphy";
794 #address-cells = <2>;
795 #size-cells = <2>;
796 ranges;
797 status = "disabled";
798
799 xphyu2port0: usb-phy@11e10000 {
800 reg = <0 0x11e10000 0 0x400>;
801 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
802 clock-names = "ref";
803 #phy-cells = <1>;
804 };
805
806 xphyu3port0: usb-phy@11e13000 {
807 reg = <0 0x11e13400 0 0x500>;
808 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
809 clock-names = "ref";
810 #phy-cells = <1>;
811 mediatek,syscon-type = <&topmisc 0x218 0>;
812 };
813 };
814
815 efuse: efuse@11f50000 {
816 compatible = "mediatek,efuse";
817 reg = <0 0x11f50000 0 0x1000>;
818 #address-cells = <1>;
819 #size-cells = <1>;
820
821 lvts_calibration: calib@918 {
822 reg = <0x918 0x28>;
823 };
824 phy_calibration_p0: calib@940 {
825 reg = <0x940 0x10>;
826 };
827 phy_calibration_p1: calib@954 {
828 reg = <0x954 0x10>;
829 };
830 phy_calibration_p2: calib@968 {
831 reg = <0x968 0x10>;
832 };
833 phy_calibration_p3: calib@97c {
834 reg = <0x97c 0x10>;
835 };
836 cpufreq_calibration: calib@278 {
837 reg = <0x278 0x1>;
838 };
839 };
840
841 ethsys: syscon@15000000 {
842 #address-cells = <1>;
843 #size-cells = <1>;
844 compatible = "mediatek,mt7988-ethsys", "syscon";
845 reg = <0 0x15000000 0 0x1000>;
846 #clock-cells = <1>;
847 #reset-cells = <1>;
848 };
849
850 switch: switch@15020000 {
851 #address-cells = <1>;
852 #size-cells = <1>;
853 compatible = "mediatek,mt7988-switch";
854 reg = <0 0x15020000 0 0x8000>;
855 interrupt-controller;
856 #interrupt-cells = <1>;
857 interrupt-parent = <&gic>;
858 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
859 resets = <&ethrst 0>;
860
861 ports {
862 #address-cells = <1>;
863 #size-cells = <0>;
864
865 port@0 {
866 reg = <0>;
867 label = "lan0";
868 phy-mode = "internal";
869 phy-handle = <&gsw_phy0>;
870 };
871
872 port@1 {
873 reg = <1>;
874 label = "lan1";
875 phy-mode = "internal";
876 phy-handle = <&gsw_phy1>;
877 };
878
879 port@2 {
880 reg = <2>;
881 label = "lan2";
882 phy-mode = "internal";
883 phy-handle = <&gsw_phy2>;
884 };
885
886 port@3 {
887 reg = <3>;
888 label = "lan3";
889 phy-mode = "internal";
890 phy-handle = <&gsw_phy3>;
891 };
892
893 port@6 {
894 reg = <6>;
895 ethernet = <&gmac0>;
896 phy-mode = "internal";
897
898 fixed-link {
899 speed = <10000>;
900 full-duplex;
901 pause;
902 };
903 };
904 };
905
906 mdio {
907 #address-cells = <1>;
908 #size-cells = <0>;
909 mediatek,pio = <&pio>;
910
911 gsw_phy0: ethernet-phy@0 {
912 compatible = "ethernet-phy-id03a2.9481";
913 reg = <0>;
914 phy-mode = "internal";
915 nvmem-cells = <&phy_calibration_p0>;
916 nvmem-cell-names = "phy-cal-data";
917
918 leds {
919 #address-cells = <1>;
920 #size-cells = <0>;
921
922 gsw_phy0_led0: gsw-phy0-led0@0 {
923 reg = <0>;
924 function = LED_FUNCTION_LAN;
925 status = "disabled";
926 };
927
928 gsw_phy0_led1: gsw-phy0-led1@1 {
929 reg = <1>;
930 function = LED_FUNCTION_LAN;
931 status = "disabled";
932 };
933 };
934 };
935
936 gsw_phy1: ethernet-phy@1 {
937 compatible = "ethernet-phy-id03a2.9481";
938 reg = <1>;
939 phy-mode = "internal";
940 nvmem-cells = <&phy_calibration_p1>;
941 nvmem-cell-names = "phy-cal-data";
942
943 leds {
944 #address-cells = <1>;
945 #size-cells = <0>;
946
947 gsw_phy1_led0: gsw-phy1-led0@0 {
948 reg = <0>;
949 function = LED_FUNCTION_LAN;
950 status = "disabled";
951 };
952
953 gsw_phy1_led1: gsw-phy1-led1@1 {
954 reg = <1>;
955 function = LED_FUNCTION_LAN;
956 status = "disabled";
957 };
958 };
959 };
960
961 gsw_phy2: ethernet-phy@2 {
962 compatible = "ethernet-phy-id03a2.9481";
963 reg = <2>;
964 phy-mode = "internal";
965 nvmem-cells = <&phy_calibration_p2>;
966 nvmem-cell-names = "phy-cal-data";
967
968 leds {
969 #address-cells = <1>;
970 #size-cells = <0>;
971
972 gsw_phy2_led0: gsw-phy2-led0@0 {
973 reg = <0>;
974 function = LED_FUNCTION_LAN;
975 status = "disabled";
976 };
977
978 gsw_phy2_led1: gsw-phy2-led1@1 {
979 reg = <1>;
980 function = LED_FUNCTION_LAN;
981 status = "disabled";
982 };
983 };
984 };
985
986 gsw_phy3: ethernet-phy@3 {
987 compatible = "ethernet-phy-id03a2.9481";
988 reg = <3>;
989 phy-mode = "internal";
990 nvmem-cells = <&phy_calibration_p3>;
991 nvmem-cell-names = "phy-cal-data";
992
993 leds {
994 #address-cells = <1>;
995 #size-cells = <0>;
996
997 gsw_phy3_led0: gsw-phy3-led0@0 {
998 reg = <0>;
999 function = LED_FUNCTION_LAN;
1000 status = "disabled";
1001 };
1002
1003 gsw_phy3_led1: gsw-phy3-led1@1 {
1004 reg = <1>;
1005 function = LED_FUNCTION_LAN;
1006 status = "disabled";
1007 };
1008 };
1009 };
1010 };
1011 };
1012
1013 ethwarp: syscon@15031000 {
1014 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
1015 reg = <0 0x15031000 0 0x1000>;
1016 #clock-cells = <1>;
1017
1018 ethrst: reset-controller {
1019 compatible = "ti,syscon-reset";
1020 #reset-cells = <1>;
1021 ti,reset-bits = <
1022 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
1023 >;
1024 };
1025 };
1026
1027 eth: ethernet@15100000 {
1028 compatible = "mediatek,mt7988-eth";
1029 reg = <0 0x15100000 0 0x80000>,
1030 <0 0x15400000 0 0x380000>;
1031 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1036 <&ethsys CLK_ETHDMA_XGP2_EN>,
1037 <&ethsys CLK_ETHDMA_XGP3_EN>,
1038 <&ethsys CLK_ETHDMA_FE_EN>,
1039 <&ethsys CLK_ETHDMA_GP2_EN>,
1040 <&ethsys CLK_ETHDMA_GP1_EN>,
1041 <&ethsys CLK_ETHDMA_GP3_EN>,
1042 <&ethsys CLK_ETHDMA_ESW_EN>,
1043 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1044 <&sgmiisys0 CLK_SGM0_TX_EN>,
1045 <&sgmiisys0 CLK_SGM0_RX_EN>,
1046 <&sgmiisys1 CLK_SGM1_TX_EN>,
1047 <&sgmiisys1 CLK_SGM1_RX_EN>,
1048 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1049 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1050 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1051 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1052 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1053 <&topckgen CLK_TOP_SGM_0_SEL>,
1054 <&topckgen CLK_TOP_SGM_1_SEL>,
1055 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
1056 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
1057 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1058 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1059 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1060 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1061 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1062 <&topckgen CLK_TOP_ETH_MII_SEL>,
1063 <&topckgen CLK_TOP_NETSYS_SEL>,
1064 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1065 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1066 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1067 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1068 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1069 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1070 "gp3", "esw", "crypto", "sgmii_tx250m",
1071 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
1072 "ethwarp_wocpu2", "ethwarp_wocpu1",
1073 "ethwarp_wocpu0", "top_usxgmii0_sel",
1074 "top_usxgmii1_sel", "top_sgm0_sel",
1075 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
1076 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
1077 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1078 "top_eth_sys_sel", "top_eth_xgmii_sel",
1079 "top_eth_mii_sel", "top_netsys_sel",
1080 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1081 "top_netsys_sync_250m_sel",
1082 "top_netsys_ppefb_250m_sel",
1083 "top_netsys_warp_sel";
1084 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1085 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1086 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1087 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1088 <&topckgen CLK_TOP_SGM_0_SEL>,
1089 <&topckgen CLK_TOP_SGM_1_SEL>;
1090 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1091 <&topckgen CLK_TOP_NET1PLL_D4>,
1092 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1093 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1094 <&apmixedsys CLK_APMIXED_SGMPLL>,
1095 <&apmixedsys CLK_APMIXED_SGMPLL>;
1096 mediatek,ethsys = <&ethsys>;
1097 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
1098 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
1099 mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
1100 mediatek,xfi_pll = <&xfi_pll>;
1101 mediatek,infracfg = <&topmisc>;
1102 mediatek,toprgu = <&watchdog>;
1103 #reset-cells = <1>;
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1106 status = "disabled";
1107
1108 gmac0: mac@0 {
1109 compatible = "mediatek,eth-mac";
1110 reg = <0>;
1111 phy-mode = "internal";
1112
1113 fixed-link {
1114 speed = <10000>;
1115 full-duplex;
1116 pause;
1117 };
1118 };
1119
1120 gmac1: mac@1 {
1121 compatible = "mediatek,eth-mac";
1122 reg = <1>;
1123 };
1124
1125 gmac2: mac@2 {
1126 compatible = "mediatek,eth-mac";
1127 reg = <2>;
1128 };
1129
1130 mdio_bus: mdio-bus {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133
1134 /* internal 2.5G PHY */
1135 int_2p5g_phy: ethernet-phy@15 {
1136 reg = <15>;
1137 compatible = "ethernet-phy-ieee802.3-c45";
1138 phy-mode = "internal";
1139 };
1140 };
1141 };
1142 };
1143 };
Staging tree of Jo-Philipp Wich