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mediatek: dts: mt7988a: wire-up mediatek,pio for PHY LEDs
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/reset/ti-syscon.h>
11 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "mediatek,mt7988";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 clk40m: oscillator@0 {
22 compatible = "fixed-clock";
23 clock-frequency = <40000000>;
24 #clock-cells = <0>;
25 clock-output-names = "clkxtal";
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31 cpu0: cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a73";
34 enable-method = "psci";
35 reg = <0x0>;
36 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
37 <&topckgen CLK_TOP_XTAL>;
38 clock-names = "cpu", "intermediate";
39 operating-points-v2 = <&cluster0_opp>;
40 mediatek,cci = <&cci>;
41 };
42
43 cpu1: cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a73";
46 enable-method = "psci";
47 reg = <0x1>;
48 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
49 <&topckgen CLK_TOP_XTAL>;
50 clock-names = "cpu", "intermediate";
51 operating-points-v2 = <&cluster0_opp>;
52 mediatek,cci = <&cci>;
53 };
54
55 cpu2: cpu@2 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a73";
58 enable-method = "psci";
59 reg = <0x2>;
60 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
61 <&topckgen CLK_TOP_XTAL>;
62 clock-names = "cpu", "intermediate";
63 operating-points-v2 = <&cluster0_opp>;
64 mediatek,cci = <&cci>;
65 };
66
67 cpu3: cpu@3 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a73";
70 enable-method = "psci";
71 reg = <0x3>;
72 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
73 <&topckgen CLK_TOP_XTAL>;
74 clock-names = "cpu", "intermediate";
75 operating-points-v2 = <&cluster0_opp>;
76 mediatek,cci = <&cci>;
77 };
78
79 cluster0_opp: opp_table0 {
80 compatible = "operating-points-v2";
81 opp-shared;
82 opp00 {
83 opp-hz = /bits/ 64 <800000000>;
84 opp-microvolt = <850000>;
85 };
86 opp01 {
87 opp-hz = /bits/ 64 <1100000000>;
88 opp-microvolt = <850000>;
89 };
90 opp02 {
91 opp-hz = /bits/ 64 <1500000000>;
92 opp-microvolt = <850000>;
93 };
94 opp03 {
95 opp-hz = /bits/ 64 <1800000000>;
96 opp-microvolt = <900000>;
97 };
98 };
99 };
100
101 cci: cci {
102 compatible = "mediatek,mt7988-cci",
103 "mediatek,mt8183-cci";
104 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
105 <&topckgen CLK_TOP_XTAL>;
106 clock-names = "cci", "intermediate";
107 operating-points-v2 = <&cci_opp>;
108 };
109
110 cci_opp: opp_table_cci {
111 compatible = "operating-points-v2";
112 opp-shared;
113 opp00 {
114 opp-hz = /bits/ 64 <480000000>;
115 opp-microvolt = <850000>;
116 };
117 opp01 {
118 opp-hz = /bits/ 64 <660000000>;
119 opp-microvolt = <850000>;
120 };
121 opp02 {
122 opp-hz = /bits/ 64 <900000000>;
123 opp-microvolt = <850000>;
124 };
125 opp03 {
126 opp-hz = /bits/ 64 <1080000000>;
127 opp-microvolt = <900000>;
128 };
129 };
130
131 pmu {
132 compatible = "arm,cortex-a73-pmu";
133 interrupt-parent = <&gic>;
134 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
135 };
136
137 psci {
138 compatible = "arm,psci-0.2";
139 method = "smc";
140 };
141
142 reserved-memory {
143 #address-cells = <2>;
144 #size-cells = <2>;
145 ranges;
146
147 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
148 secmon_reserved: secmon@43000000 {
149 reg = <0 0x43000000 0 0x30000>;
150 no-map;
151 };
152 };
153
154 timer {
155 compatible = "arm,armv8-timer";
156 interrupt-parent = <&gic>;
157 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
158 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
159 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
160 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
161 };
162
163 soc {
164 #address-cells = <2>;
165 #size-cells = <2>;
166 compatible = "simple-bus";
167 ranges;
168
169 gic: interrupt-controller@c000000 {
170 compatible = "arm,gic-v3";
171 #interrupt-cells = <3>;
172 interrupt-parent = <&gic>;
173 interrupt-controller;
174 reg = <0 0x0c000000 0 0x40000>, /* GICD */
175 <0 0x0c080000 0 0x200000>, /* GICR */
176 <0 0x0c400000 0 0x2000>, /* GICC */
177 <0 0x0c410000 0 0x1000>, /* GICH */
178 <0 0x0c420000 0 0x2000>; /* GICV */
179
180 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
181 };
182
183 phyfw: phy-firmware@f000000 {
184 compatible = "mediatek,2p5gphy-fw";
185 reg = <0 0x0f000000 0 0x8000>,
186 <0 0x0f100000 0 0x20000>,
187 <0 0x0f0f0000 0 0x200>;
188 };
189
190 infracfg: infracfg@10001000 {
191 compatible = "mediatek,mt7988-infracfg", "syscon";
192 reg = <0 0x10001000 0 0x1000>;
193 #clock-cells = <1>;
194 };
195
196 topckgen: topckgen@1001b000 {
197 compatible = "mediatek,mt7988-topckgen", "syscon";
198 reg = <0 0x1001b000 0 0x1000>;
199 #clock-cells = <1>;
200 };
201
202 watchdog: watchdog@1001c000 {
203 compatible = "mediatek,mt7988-wdt",
204 "mediatek,mt6589-wdt",
205 "syscon";
206 reg = <0 0x1001c000 0 0x1000>;
207 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
208 #reset-cells = <1>;
209 };
210
211 apmixedsys: apmixedsys@1001e000 {
212 compatible = "mediatek,mt7988-apmixedsys";
213 reg = <0 0x1001e000 0 0x1000>;
214 #clock-cells = <1>;
215 };
216
217 pio: pinctrl@1001f000 {
218 compatible = "mediatek,mt7988-pinctrl", "syscon";
219 reg = <0 0x1001f000 0 0x1000>,
220 <0 0x11c10000 0 0x1000>,
221 <0 0x11d00000 0 0x1000>,
222 <0 0x11d20000 0 0x1000>,
223 <0 0x11e00000 0 0x1000>,
224 <0 0x11f00000 0 0x1000>,
225 <0 0x1000b000 0 0x1000>;
226 reg-names = "gpio_base", "iocfg_tr_base",
227 "iocfg_br_base", "iocfg_rb_base",
228 "iocfg_lb_base", "iocfg_tl_base", "eint";
229 gpio-controller;
230 #gpio-cells = <2>;
231 gpio-ranges = <&pio 0 0 83>;
232 interrupt-controller;
233 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
234 interrupt-parent = <&gic>;
235 #interrupt-cells = <2>;
236
237 mdio0_pins: mdio0-pins {
238 mux {
239 function = "eth";
240 groups = "mdc_mdio0";
241 };
242
243 conf {
244 groups = "mdc_mdio0";
245 drive-strength = <MTK_DRIVE_8mA>;
246 };
247 };
248
249 i2c0_pins: i2c0-pins-g0 {
250 mux {
251 function = "i2c";
252 groups = "i2c0_1";
253 };
254 };
255
256 i2c1_pins: i2c1-pins-g0 {
257 mux {
258 function = "i2c";
259 groups = "i2c1_0";
260 };
261 };
262
263 i2c2_pins: i2c2-pins-g0 {
264 mux {
265 function = "i2c";
266 groups = "i2c2_1";
267 };
268 };
269
270 gbe0_led0_pins: gbe0-pins {
271 mux {
272 function = "led";
273 groups = "gbe0_led0";
274 };
275 };
276
277 gbe1_led0_pins: gbe1-pins {
278 mux {
279 function = "led";
280 groups = "gbe1_led0";
281 };
282 };
283
284 gbe2_led0_pins: gbe2-pins {
285 mux {
286 function = "led";
287 groups = "gbe2_led0";
288 };
289 };
290
291 gbe3_led0_pins: gbe3-pins {
292 mux {
293 function = "led";
294 groups = "gbe3_led0";
295 };
296 };
297
298 i2p5gbe_led0_pins: 2p5gbe-pins {
299 mux {
300 function = "led";
301 groups = "2p5gbe_led0";
302 };
303 };
304 };
305
306 boottrap: boottrap@1001f6f0 {
307 compatible = "mediatek,boottrap";
308 reg = <0 0x1001f6f0 0 0x4>;
309 };
310
311 sgmiisys0: syscon@10060000 {
312 compatible = "mediatek,mt7988-sgmiisys",
313 "mediatek,mt7988-sgmiisys_0",
314 "syscon";
315 reg = <0 0x10060000 0 0x1000>;
316 #clock-cells = <1>;
317 };
318
319 sgmiisys1: syscon@10070000 {
320 compatible = "mediatek,mt7988-sgmiisys",
321 "mediatek,mt7988-sgmiisys_1",
322 "syscon";
323 reg = <0 0x10070000 0 0x1000>;
324 #clock-cells = <1>;
325 };
326
327 usxgmiisys0: usxgmiisys@10080000 {
328 compatible = "mediatek,mt7988-usxgmiisys",
329 "mediatek,mt7988-usxgmiisys_0",
330 "syscon";
331 reg = <0 0x10080000 0 0x1000>;
332 #clock-cells = <1>;
333 };
334
335 usxgmiisys1: usxgmiisys@10081000 {
336 compatible = "mediatek,mt7988-usxgmiisys",
337 "mediatek,mt7988-usxgmiisys_1",
338 "syscon";
339 reg = <0 0x10081000 0 0x1000>;
340 #clock-cells = <1>;
341 };
342
343 xfi_pextp0: xfi_pextp@11f20000 {
344 compatible = "mediatek,mt7988-xfi_pextp",
345 "mediatek,mt7988-xfi_pextp_0",
346 "syscon";
347 reg = <0 0x11f20000 0 0x10000>;
348 #clock-cells = <1>;
349 };
350
351 xfi_pextp1: xfi_pextp@11f30000 {
352 compatible = "mediatek,mt7988-xfi_pextp",
353 "mediatek,mt7988-xfi_pextp_1",
354 "syscon";
355 reg = <0 0x11f30000 0 0x10000>;
356 #clock-cells = <1>;
357 };
358
359 xfi_pll: xfi_pll@11f40000 {
360 compatible = "mediatek,mt7988-xfi_pll", "syscon";
361 reg = <0 0x11f40000 0 0x1000>;
362 #clock-cells = <1>;
363 };
364
365 mcusys: mcusys@100e0000 {
366 compatible = "mediatek,mt7988-mcusys", "syscon";
367 reg = <0 0x100e0000 0 0x1000>;
368 #clock-cells = <1>;
369 };
370
371 uart0: serial@11000000 {
372 compatible = "mediatek,mt7986-uart",
373 "mediatek,mt6577-uart";
374 reg = <0 0x11000000 0 0x100>;
375 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
376 /*
377 * 8250-mtk driver don't control "baud" clock since commit
378 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
379 * still need to be passed to the driver to prevent probe fail
380 */
381 clocks = <&topckgen CLK_TOP_UART_SEL>,
382 <&infracfg CLK_INFRA_52M_UART0_CK>;
383 clock-names = "baud", "bus";
384 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
385 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
386 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
387 <&topckgen CLK_TOP_UART_SEL>;
388 status = "disabled";
389 };
390
391 i2c0: i2c@11003000 {
392 compatible = "mediatek,mt7988-i2c",
393 "mediatek,mt7981-i2c";
394 reg = <0 0x11003000 0 0x1000>,
395 <0 0x10217080 0 0x80>;
396 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
397 clock-div = <1>;
398 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
399 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
400 clock-names = "main", "dma";
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
405
406 i2c1: i2c@11004000 {
407 compatible = "mediatek,mt7988-i2c",
408 "mediatek,mt7981-i2c";
409 reg = <0 0x11004000 0 0x1000>,
410 <0 0x10217100 0 0x80>;
411 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
412 clock-div = <1>;
413 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
414 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
415 clock-names = "main", "dma";
416 #address-cells = <1>;
417 #size-cells = <0>;
418 status = "disabled";
419 };
420
421 i2c2: i2c@11005000 {
422 compatible = "mediatek,mt7988-i2c",
423 "mediatek,mt7981-i2c";
424 reg = <0 0x11005000 0 0x1000>,
425 <0 0x10217180 0 0x80>;
426 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
427 clock-div = <1>;
428 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
429 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
430 clock-names = "main", "dma";
431 #address-cells = <1>;
432 #size-cells = <0>;
433 status = "disabled";
434 };
435
436 spi0: spi@11007000 {
437 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
438 reg = <0 0x11007000 0 0x100>;
439 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&topckgen CLK_TOP_MPLL_D2>,
441 <&topckgen CLK_TOP_SPI_SEL>,
442 <&infracfg CLK_INFRA_104M_SPI0>,
443 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
444 clock-names = "parent-clk", "sel-clk", "spi-clk",
445 "spi-hclk";
446
447 #address-cells = <1>;
448 #size-cells = <0>;
449
450 status = "disabled";
451 };
452
453 pcie2: pcie@11280000 {
454 compatible = "mediatek,mt7988-pcie",
455 "mediatek,mt7986-pcie",
456 "mediatek,mt8192-pcie";
457 device_type = "pci";
458 #address-cells = <3>;
459 #size-cells = <2>;
460 reg = <0 0x11280000 0 0x2000>;
461 reg-names = "pcie-mac";
462 linux,pci-domain = <3>;
463 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
464 bus-range = <0x00 0xff>;
465 ranges = <0x81000000 0x00 0x20000000 0x00
466 0x20000000 0x00 0x00200000>,
467 <0x82000000 0x00 0x20200000 0x00
468 0x20200000 0x00 0x07e00000>;
469 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
470 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
471 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
472 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
473 clock-names = "pl_250m", "tl_26m", "peri_26m",
474 "top_133m";
475 status = "disabled";
476
477 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
478 phy-names = "pcie-phy";
479
480 #interrupt-cells = <1>;
481 interrupt-map-mask = <0 0 0 0x7>;
482 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
483 <0 0 0 2 &pcie_intc2 1>,
484 <0 0 0 3 &pcie_intc2 2>,
485 <0 0 0 4 &pcie_intc2 3>;
486 pcie_intc2: interrupt-controller {
487 #address-cells = <0>;
488 #interrupt-cells = <1>;
489 interrupt-controller;
490 };
491 };
492
493 pcie3: pcie@11290000 {
494 compatible = "mediatek,mt7988-pcie",
495 "mediatek,mt7986-pcie",
496 "mediatek,mt8192-pcie";
497 device_type = "pci";
498 #address-cells = <3>;
499 #size-cells = <2>;
500 reg = <0 0x11290000 0 0x2000>;
501 reg-names = "pcie-mac";
502 linux,pci-domain = <2>;
503 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
504 bus-range = <0x00 0xff>;
505 ranges = <0x81000000 0x00 0x28000000 0x00
506 0x28000000 0x00 0x00200000>,
507 <0x82000000 0x00 0x28200000 0x00
508 0x28200000 0x00 0x07e00000>;
509 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
510 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
511 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
512 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
513 clock-names = "pl_250m", "tl_26m", "peri_26m",
514 "top_133m";
515 status = "disabled";
516
517 #interrupt-cells = <1>;
518 interrupt-map-mask = <0 0 0 0x7>;
519 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
520 <0 0 0 2 &pcie_intc3 1>,
521 <0 0 0 3 &pcie_intc3 2>,
522 <0 0 0 4 &pcie_intc3 3>;
523 pcie_intc3: interrupt-controller {
524 #address-cells = <0>;
525 #interrupt-cells = <1>;
526 interrupt-controller;
527 };
528 };
529
530 pcie0: pcie@11300000 {
531 compatible = "mediatek,mt7988-pcie",
532 "mediatek,mt7986-pcie",
533 "mediatek,mt8192-pcie";
534 device_type = "pci";
535 #address-cells = <3>;
536 #size-cells = <2>;
537 reg = <0 0x11300000 0 0x2000>;
538 reg-names = "pcie-mac";
539 linux,pci-domain = <0>;
540 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
541 bus-range = <0x00 0xff>;
542 ranges = <0x81000000 0x00 0x30000000 0x00
543 0x30000000 0x00 0x00200000>,
544 <0x82000000 0x00 0x30200000 0x00
545 0x30200000 0x00 0x07e00000>;
546 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
547 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
548 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
549 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
550 clock-names = "pl_250m", "tl_26m", "peri_26m",
551 "top_133m";
552 status = "disabled";
553
554 #interrupt-cells = <1>;
555 interrupt-map-mask = <0 0 0 0x7>;
556 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
557 <0 0 0 2 &pcie_intc0 1>,
558 <0 0 0 3 &pcie_intc0 2>,
559 <0 0 0 4 &pcie_intc0 3>;
560 pcie_intc0: interrupt-controller {
561 #address-cells = <0>;
562 #interrupt-cells = <1>;
563 interrupt-controller;
564 };
565 };
566
567 pcie1: pcie@11310000 {
568 compatible = "mediatek,mt7988-pcie",
569 "mediatek,mt7986-pcie",
570 "mediatek,mt8192-pcie";
571 device_type = "pci";
572 #address-cells = <3>;
573 #size-cells = <2>;
574 reg = <0 0x11310000 0 0x2000>;
575 reg-names = "pcie-mac";
576 linux,pci-domain = <1>;
577 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
578 bus-range = <0x00 0xff>;
579 ranges = <0x81000000 0x00 0x38000000 0x00
580 0x38000000 0x00 0x00200000>,
581 <0x82000000 0x00 0x38200000 0x00
582 0x38200000 0x00 0x07e00000>;
583 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
584 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
585 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
586 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
587 clock-names = "pl_250m", "tl_26m", "peri_26m",
588 "top_133m";
589 status = "disabled";
590
591 #interrupt-cells = <1>;
592 interrupt-map-mask = <0 0 0 0x7>;
593 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
594 <0 0 0 2 &pcie_intc1 1>,
595 <0 0 0 3 &pcie_intc1 2>,
596 <0 0 0 4 &pcie_intc1 3>;
597 pcie_intc1: interrupt-controller {
598 #address-cells = <0>;
599 #interrupt-cells = <1>;
600 interrupt-controller;
601 };
602 };
603
604 ssusb0: usb@11190000 {
605 compatible = "mediatek,mt7988-xhci",
606 "mediatek,mtk-xhci";
607 reg = <0 0x11190000 0 0x2e00>,
608 <0 0x11193e00 0 0x0100>;
609 reg-names = "mac", "ippc";
610 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
611 phys = <&xphyu2port0 PHY_TYPE_USB2>,
612 <&xphyu3port0 PHY_TYPE_USB3>;
613 clocks = <&infracfg CLK_INFRA_USB_SYS>,
614 <&infracfg CLK_INFRA_USB_XHCI>,
615 <&infracfg CLK_INFRA_USB_REF>,
616 <&infracfg CLK_INFRA_66M_USB_HCK>,
617 <&infracfg CLK_INFRA_133M_USB_HCK>;
618 clock-names = "sys_ck",
619 "xhci_ck",
620 "ref_ck",
621 "mcu_ck",
622 "dma_ck";
623 #address-cells = <2>;
624 #size-cells = <2>;
625 mediatek,p0_speed_fixup;
626 status = "disabled";
627 };
628
629 ssusb1: usb@11200000 {
630 compatible = "mediatek,mt7988-xhci",
631 "mediatek,mtk-xhci";
632 reg = <0 0x11200000 0 0x2e00>,
633 <0 0x11203e00 0 0x0100>;
634 reg-names = "mac", "ippc";
635 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
636 phys = <&tphyu2port0 PHY_TYPE_USB2>,
637 <&tphyu3port0 PHY_TYPE_USB3>;
638 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
639 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
640 <&infracfg CLK_INFRA_USB_CK_P1>,
641 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
642 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
643 clock-names = "sys_ck",
644 "xhci_ck",
645 "ref_ck",
646 "mcu_ck",
647 "dma_ck";
648 #address-cells = <2>;
649 #size-cells = <2>;
650 status = "disabled";
651 };
652
653 tphy: tphy@11c50000 {
654 compatible = "mediatek,mt7988",
655 "mediatek,generic-tphy-v2";
656 #address-cells = <2>;
657 #size-cells = <2>;
658 ranges;
659 status = "disabled";
660 tphyu2port0: usb-phy@11c50000 {
661 reg = <0 0x11c50000 0 0x700>;
662 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
663 clock-names = "ref";
664 #phy-cells = <1>;
665 };
666 tphyu3port0: usb-phy@11c50700 {
667 reg = <0 0x11c50700 0 0x900>;
668 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
669 clock-names = "ref";
670 #phy-cells = <1>;
671 mediatek,usb3-pll-ssc-delta;
672 mediatek,usb3-pll-ssc-delta1;
673 };
674 };
675
676 topmisc: topmisc@11d10000 {
677 compatible = "mediatek,mt7988-topmisc", "syscon",
678 "mediatek,mt7988-power-controller";
679 reg = <0 0x11d10000 0 0x10000>;
680 #clock-cells = <1>;
681 #power-domain-cells = <1>;
682 #address-cells = <1>;
683 #size-cells = <0>;
684 };
685
686 xphy: xphy@11e10000 {
687 compatible = "mediatek,mt7988",
688 "mediatek,xsphy";
689 #address-cells = <2>;
690 #size-cells = <2>;
691 ranges;
692 status = "disabled";
693
694 xphyu2port0: usb-phy@11e10000 {
695 reg = <0 0x11e10000 0 0x400>;
696 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
697 clock-names = "ref";
698 #phy-cells = <1>;
699 };
700
701 xphyu3port0: usb-phy@11e13000 {
702 reg = <0 0x11e13400 0 0x500>;
703 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
704 clock-names = "ref";
705 #phy-cells = <1>;
706 mediatek,syscon-type = <&topmisc 0x218 0>;
707 };
708 };
709
710 efuse: efuse@11f50000 {
711 compatible = "mediatek,efuse";
712 reg = <0 0x11f50000 0 0x1000>;
713 #address-cells = <1>;
714 #size-cells = <1>;
715
716 lvts_calibration: calib@918 {
717 reg = <0x918 0x28>;
718 };
719 phy_calibration_p0: calib@940 {
720 reg = <0x940 0x10>;
721 };
722 phy_calibration_p1: calib@954 {
723 reg = <0x954 0x10>;
724 };
725 phy_calibration_p2: calib@968 {
726 reg = <0x968 0x10>;
727 };
728 phy_calibration_p3: calib@97c {
729 reg = <0x97c 0x10>;
730 };
731 cpufreq_calibration: calib@278 {
732 reg = <0x278 0x1>;
733 };
734 };
735
736 ethsys: syscon@15000000 {
737 #address-cells = <1>;
738 #size-cells = <1>;
739 compatible = "mediatek,mt7988-ethsys", "syscon";
740 reg = <0 0x15000000 0 0x1000>;
741 #clock-cells = <1>;
742 #reset-cells = <1>;
743 };
744
745 switch: switch@15020000 {
746 #address-cells = <1>;
747 #size-cells = <1>;
748 compatible = "mediatek,mt7988-switch";
749 reg = <0 0x15020000 0 0x8000>;
750 interrupt-controller;
751 #interrupt-cells = <1>;
752 interrupt-parent = <&gic>;
753 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
754 resets = <&ethrst 0>;
755 };
756
757 ethwarp: syscon@15031000 {
758 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
759 reg = <0 0x15031000 0 0x1000>;
760 #clock-cells = <1>;
761
762 ethrst: reset-controller {
763 compatible = "ti,syscon-reset";
764 #reset-cells = <1>;
765 ti,reset-bits = <
766 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
767 >;
768 };
769 };
770
771 eth: ethernet@15100000 {
772 compatible = "mediatek,mt7988-eth";
773 reg = <0 0x15100000 0 0x80000>,
774 <0 0x15400000 0 0x380000>;
775 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
780 <&ethsys CLK_ETHDMA_XGP2_EN>,
781 <&ethsys CLK_ETHDMA_XGP3_EN>,
782 <&ethsys CLK_ETHDMA_FE_EN>,
783 <&ethsys CLK_ETHDMA_GP2_EN>,
784 <&ethsys CLK_ETHDMA_GP1_EN>,
785 <&ethsys CLK_ETHDMA_GP3_EN>,
786 <&ethsys CLK_ETHDMA_ESW_EN>,
787 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
788 <&sgmiisys0 CLK_SGM0_TX_EN>,
789 <&sgmiisys0 CLK_SGM0_RX_EN>,
790 <&sgmiisys1 CLK_SGM1_TX_EN>,
791 <&sgmiisys1 CLK_SGM1_RX_EN>,
792 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
793 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
794 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
795 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
796 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
797 <&topckgen CLK_TOP_SGM_0_SEL>,
798 <&topckgen CLK_TOP_SGM_1_SEL>,
799 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
800 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
801 <&topckgen CLK_TOP_ETH_GMII_SEL>,
802 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
803 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
804 <&topckgen CLK_TOP_ETH_SYS_SEL>,
805 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
806 <&topckgen CLK_TOP_ETH_MII_SEL>,
807 <&topckgen CLK_TOP_NETSYS_SEL>,
808 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
809 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
810 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
811 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
812 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
813 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
814 "gp3", "esw", "crypto", "sgmii_tx250m",
815 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
816 "ethwarp_wocpu2", "ethwarp_wocpu1",
817 "ethwarp_wocpu0", "top_usxgmii0_sel",
818 "top_usxgmii1_sel", "top_sgm0_sel",
819 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
820 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
821 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
822 "top_eth_sys_sel", "top_eth_xgmii_sel",
823 "top_eth_mii_sel", "top_netsys_sel",
824 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
825 "top_netsys_sync_250m_sel",
826 "top_netsys_ppefb_250m_sel",
827 "top_netsys_warp_sel";
828 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
829 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
830 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
831 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
832 <&topckgen CLK_TOP_SGM_0_SEL>,
833 <&topckgen CLK_TOP_SGM_1_SEL>;
834 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
835 <&topckgen CLK_TOP_NET1PLL_D4>,
836 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
837 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
838 <&apmixedsys CLK_APMIXED_SGMPLL>,
839 <&apmixedsys CLK_APMIXED_SGMPLL>;
840 mediatek,ethsys = <&ethsys>;
841 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
842 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
843 mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
844 mediatek,xfi_pll = <&xfi_pll>;
845 mediatek,infracfg = <&topmisc>;
846 mediatek,toprgu = <&watchdog>;
847 #reset-cells = <1>;
848 #address-cells = <1>;
849 #size-cells = <0>;
850 status = "disabled";
851 };
852 };
853 };
Staging tree of Jo-Philipp Wich