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mediatek: generate bootloader artifacts for mt7988_rfb
[openwrt/staging/stintel.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/ti-syscon.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 compatible = "mediatek,mt7988";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 clk40m: oscillator@0 {
23 compatible = "fixed-clock";
24 clock-frequency = <40000000>;
25 #clock-cells = <0>;
26 clock-output-names = "clkxtal";
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32 cpu0: cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a73";
35 enable-method = "psci";
36 reg = <0x0>;
37 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
38 <&topckgen CLK_TOP_XTAL>;
39 clock-names = "cpu", "intermediate";
40 operating-points-v2 = <&cluster0_opp>;
41 mediatek,cci = <&cci>;
42 };
43
44 cpu1: cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a73";
47 enable-method = "psci";
48 reg = <0x1>;
49 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
50 <&topckgen CLK_TOP_XTAL>;
51 clock-names = "cpu", "intermediate";
52 operating-points-v2 = <&cluster0_opp>;
53 mediatek,cci = <&cci>;
54 };
55
56 cpu2: cpu@2 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a73";
59 enable-method = "psci";
60 reg = <0x2>;
61 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
62 <&topckgen CLK_TOP_XTAL>;
63 clock-names = "cpu", "intermediate";
64 operating-points-v2 = <&cluster0_opp>;
65 mediatek,cci = <&cci>;
66 };
67
68 cpu3: cpu@3 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a73";
71 enable-method = "psci";
72 reg = <0x3>;
73 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
74 <&topckgen CLK_TOP_XTAL>;
75 clock-names = "cpu", "intermediate";
76 operating-points-v2 = <&cluster0_opp>;
77 mediatek,cci = <&cci>;
78 };
79
80 cluster0_opp: opp_table0 {
81 compatible = "operating-points-v2";
82 opp-shared;
83 opp00 {
84 opp-hz = /bits/ 64 <800000000>;
85 opp-microvolt = <850000>;
86 };
87 opp01 {
88 opp-hz = /bits/ 64 <1100000000>;
89 opp-microvolt = <850000>;
90 };
91 opp02 {
92 opp-hz = /bits/ 64 <1500000000>;
93 opp-microvolt = <850000>;
94 };
95 opp03 {
96 opp-hz = /bits/ 64 <1800000000>;
97 opp-microvolt = <900000>;
98 };
99 };
100 };
101
102 cci: cci {
103 compatible = "mediatek,mt7988-cci",
104 "mediatek,mt8183-cci";
105 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
106 <&topckgen CLK_TOP_XTAL>;
107 clock-names = "cci", "intermediate";
108 operating-points-v2 = <&cci_opp>;
109 };
110
111 cci_opp: opp_table_cci {
112 compatible = "operating-points-v2";
113 opp-shared;
114 opp00 {
115 opp-hz = /bits/ 64 <480000000>;
116 opp-microvolt = <850000>;
117 };
118 opp01 {
119 opp-hz = /bits/ 64 <660000000>;
120 opp-microvolt = <850000>;
121 };
122 opp02 {
123 opp-hz = /bits/ 64 <900000000>;
124 opp-microvolt = <850000>;
125 };
126 opp03 {
127 opp-hz = /bits/ 64 <1080000000>;
128 opp-microvolt = <900000>;
129 };
130 };
131
132 pmu {
133 compatible = "arm,cortex-a73-pmu";
134 interrupt-parent = <&gic>;
135 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
136 };
137
138 psci {
139 compatible = "arm,psci-0.2";
140 method = "smc";
141 };
142
143 reserved-memory {
144 #address-cells = <2>;
145 #size-cells = <2>;
146 ranges;
147
148 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
149 secmon_reserved: secmon@43000000 {
150 reg = <0 0x43000000 0 0x50000>;
151 no-map;
152 };
153 };
154
155 thermal-zones {
156 cpu_thermal: cpu-thermal {
157 polling-delay-passive = <1000>;
158 polling-delay = <1000>;
159 thermal-sensors = <&lvts 0>;
160 trips {
161 cpu_trip_crit: crit {
162 temperature = <125000>;
163 hysteresis = <2000>;
164 type = "critical";
165 };
166
167 cpu_trip_hot: hot {
168 temperature = <120000>;
169 hysteresis = <2000>;
170 type = "hot";
171 };
172
173 cpu_trip_active_high: active-high {
174 temperature = <115000>;
175 hysteresis = <2000>;
176 type = "active";
177 };
178
179 cpu_trip_active_med: active-med {
180 temperature = <85000>;
181 hysteresis = <2000>;
182 type = "active";
183 };
184
185 cpu_trip_active_low: active-low {
186 temperature = <40000>;
187 hysteresis = <2000>;
188 type = "active";
189 };
190 };
191
192 cooling-maps {
193 cpu-active-high {
194 /* active: set fan to cooling level 2 */
195 cooling-device = <&fan 3 3>;
196 trip = <&cpu_trip_active_high>;
197 };
198
199 cpu-active-low {
200 /* active: set fan to cooling level 1 */
201 cooling-device = <&fan 2 2>;
202 trip = <&cpu_trip_active_med>;
203 };
204
205 cpu-passive {
206 /* passive: set fan to cooling level 0 */
207 cooling-device = <&fan 1 1>;
208 trip = <&cpu_trip_active_low>;
209 };
210 };
211 };
212 };
213
214 timer {
215 compatible = "arm,armv8-timer";
216 interrupt-parent = <&gic>;
217 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
218 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
221 };
222
223 reg_1p8v: regulator-1p8v {
224 compatible = "regulator-fixed";
225 regulator-name = "fixed-1.8V";
226 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <1800000>;
228 regulator-boot-on;
229 regulator-always-on;
230 };
231
232 reg_3p3v: regulator-3p3v {
233 compatible = "regulator-fixed";
234 regulator-name = "fixed-3.3V";
235 regulator-min-microvolt = <3300000>;
236 regulator-max-microvolt = <3300000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 soc {
242 #address-cells = <2>;
243 #size-cells = <2>;
244 compatible = "simple-bus";
245 ranges;
246
247 gic: interrupt-controller@c000000 {
248 compatible = "arm,gic-v3";
249 #interrupt-cells = <3>;
250 interrupt-parent = <&gic>;
251 interrupt-controller;
252 reg = <0 0x0c000000 0 0x40000>, /* GICD */
253 <0 0x0c080000 0 0x200000>, /* GICR */
254 <0 0x0c400000 0 0x2000>, /* GICC */
255 <0 0x0c410000 0 0x1000>, /* GICH */
256 <0 0x0c420000 0 0x2000>; /* GICV */
257
258 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
259 };
260
261 phyfw: phy-firmware@f000000 {
262 compatible = "mediatek,2p5gphy-fw";
263 reg = <0 0x0f000000 0 0x8000>,
264 <0 0x0f100000 0 0x20000>,
265 <0 0x0f0f0000 0 0x200>;
266 };
267
268 infracfg: infracfg@10001000 {
269 compatible = "mediatek,mt7988-infracfg", "syscon";
270 reg = <0 0x10001000 0 0x1000>;
271 #clock-cells = <1>;
272 };
273
274 topckgen: topckgen@1001b000 {
275 compatible = "mediatek,mt7988-topckgen", "syscon";
276 reg = <0 0x1001b000 0 0x1000>;
277 #clock-cells = <1>;
278 };
279
280 watchdog: watchdog@1001c000 {
281 compatible = "mediatek,mt7988-wdt",
282 "mediatek,mt6589-wdt",
283 "syscon";
284 reg = <0 0x1001c000 0 0x1000>;
285 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
286 #reset-cells = <1>;
287 };
288
289 apmixedsys: apmixedsys@1001e000 {
290 compatible = "mediatek,mt7988-apmixedsys";
291 reg = <0 0x1001e000 0 0x1000>;
292 #clock-cells = <1>;
293 };
294
295 pio: pinctrl@1001f000 {
296 compatible = "mediatek,mt7988-pinctrl", "syscon";
297 reg = <0 0x1001f000 0 0x1000>,
298 <0 0x11c10000 0 0x1000>,
299 <0 0x11d00000 0 0x1000>,
300 <0 0x11d20000 0 0x1000>,
301 <0 0x11e00000 0 0x1000>,
302 <0 0x11f00000 0 0x1000>,
303 <0 0x1000b000 0 0x1000>;
304 reg-names = "gpio_base", "iocfg_tr_base",
305 "iocfg_br_base", "iocfg_rb_base",
306 "iocfg_lb_base", "iocfg_tl_base", "eint";
307 gpio-controller;
308 #gpio-cells = <2>;
309 gpio-ranges = <&pio 0 0 84>;
310 interrupt-controller;
311 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-parent = <&gic>;
313 #interrupt-cells = <2>;
314
315 mdio0_pins: mdio0-pins {
316 mux {
317 function = "eth";
318 groups = "mdc_mdio0";
319 };
320
321 conf {
322 groups = "mdc_mdio0";
323 drive-strength = <MTK_DRIVE_8mA>;
324 };
325 };
326
327 i2c0_pins: i2c0-pins-g0 {
328 mux {
329 function = "i2c";
330 groups = "i2c0_1";
331 };
332 };
333
334 i2c1_pins: i2c1-pins-g0 {
335 mux {
336 function = "i2c";
337 groups = "i2c1_0";
338 };
339 };
340
341 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
342 mux {
343 function = "i2c";
344 groups = "i2c1_sfp";
345 };
346 };
347
348 i2c2_pins: i2c2-pins {
349 mux {
350 function = "i2c";
351 groups = "i2c2";
352 };
353 };
354
355 i2c2_0_pins: i2c2-pins-g0 {
356 mux {
357 function = "i2c";
358 groups = "i2c2_0";
359 };
360 };
361
362 i2c2_1_pins: i2c2-pins-g1 {
363 mux {
364 function = "i2c";
365 groups = "i2c2_1";
366 };
367 };
368
369 gbe0_led0_pins: gbe0-led0-pins {
370 mux {
371 function = "led";
372 groups = "gbe0_led0";
373 };
374 };
375
376 gbe1_led0_pins: gbe1-led0-pins {
377 mux {
378 function = "led";
379 groups = "gbe1_led0";
380 };
381 };
382
383 gbe2_led0_pins: gbe2-led0-pins {
384 mux {
385 function = "led";
386 groups = "gbe2_led0";
387 };
388 };
389
390 gbe3_led0_pins: gbe3-led0-pins {
391 mux {
392 function = "led";
393 groups = "gbe3_led0";
394 };
395 };
396
397 gbe0_led1_pins: gbe0-led1-pins {
398 mux {
399 function = "led";
400 groups = "gbe0_led1";
401 };
402 };
403
404 gbe1_led1_pins: gbe1-led1-pins {
405 mux {
406 function = "led";
407 groups = "gbe1_led1";
408 };
409 };
410
411 gbe2_led1_pins: gbe2-led1-pins {
412 mux {
413 function = "led";
414 groups = "gbe2_led1";
415 };
416 };
417
418 gbe3_led1_pins: gbe3-led1-pins {
419 mux {
420 function = "led";
421 groups = "gbe3_led1";
422 };
423 };
424
425 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
426 mux {
427 function = "led";
428 groups = "2p5gbe_led0";
429 };
430 };
431
432 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
433 mux {
434 function = "led";
435 groups = "2p5gbe_led1";
436 };
437 };
438
439 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
440 mux {
441 function = "flash";
442 groups = "emmc_45";
443 };
444 };
445
446 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
447 mux {
448 function = "flash";
449 groups = "emmc_51";
450 };
451 };
452
453 mmc0_pins_sdcard: mmc0-pins-sdcard {
454 mux {
455 function = "flash";
456 groups = "sdcard";
457 };
458 };
459
460 uart0_pins: uart0-pins {
461 mux {
462 function = "uart";
463 groups = "uart0";
464 };
465 };
466
467 snfi_pins: snfi-pins {
468 mux {
469 function = "flash";
470 groups = "snfi";
471 };
472 };
473
474 spi0_pins: spi0-pins {
475 mux {
476 function = "spi";
477 groups = "spi0";
478 };
479 };
480
481 spi0_flash_pins: spi0-flash-pins {
482 mux {
483 function = "spi";
484 groups = "spi0", "spi0_wp_hold";
485 };
486 };
487
488 spi1_pins: spi1-pins {
489 mux {
490 function = "spi";
491 groups = "spi1";
492 };
493 };
494
495 spi2_pins: spi2-pins {
496 mux {
497 function = "spi";
498 groups = "spi2";
499 };
500 };
501
502 spi2_flash_pins: spi2-flash-pins {
503 mux {
504 function = "spi";
505 groups = "spi2", "spi2_wp_hold";
506 };
507 };
508
509 pcie0_pins: pcie0-pins {
510 mux {
511 function = "pcie";
512 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
513 "pcie_wake_n0_0";
514 };
515 };
516
517 pcie1_pins: pcie1-pins {
518 mux {
519 function = "pcie";
520 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
521 "pcie_wake_n1_0";
522 };
523 };
524
525 pcie2_pins: pcie2-pins {
526 mux {
527 function = "pcie";
528 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
529 "pcie_wake_n2_0";
530 };
531 };
532
533 pcie3_pins: pcie3-pins {
534 mux {
535 function = "pcie";
536 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
537 "pcie_wake_n3_0";
538 };
539 };
540 };
541
542 sgmiisys0: syscon@10060000 {
543 compatible = "mediatek,mt7988-sgmiisys",
544 "mediatek,mt7988-sgmiisys_0",
545 "syscon";
546 reg = <0 0x10060000 0 0x1000>;
547 #clock-cells = <1>;
548 };
549
550 sgmiisys1: syscon@10070000 {
551 compatible = "mediatek,mt7988-sgmiisys",
552 "mediatek,mt7988-sgmiisys_1",
553 "syscon";
554 reg = <0 0x10070000 0 0x1000>;
555 #clock-cells = <1>;
556 };
557
558 usxgmiisys0: usxgmiisys@10080000 {
559 compatible = "mediatek,mt7988-usxgmiisys",
560 "mediatek,mt7988-usxgmiisys_0",
561 "syscon";
562 reg = <0 0x10080000 0 0x1000>;
563 #clock-cells = <1>;
564 };
565
566 usxgmiisys1: usxgmiisys@10081000 {
567 compatible = "mediatek,mt7988-usxgmiisys",
568 "mediatek,mt7988-usxgmiisys_1",
569 "syscon";
570 reg = <0 0x10081000 0 0x1000>;
571 #clock-cells = <1>;
572 };
573
574 xfi_pextp0: xfi-pextp@11f20000 {
575 compatible = "mediatek,mt7988-xfi-pextp",
576 "mediatek,mt7988-xfi-pextp_0",
577 "syscon";
578 reg = <0 0x11f20000 0 0x10000>;
579 #clock-cells = <1>;
580 };
581
582 xfi_pextp1: xfi-pextp@11f30000 {
583 compatible = "mediatek,mt7988-xfi-pextp",
584 "mediatek,mt7988-xfi-pextp_1",
585 "syscon";
586 reg = <0 0x11f30000 0 0x10000>;
587 #clock-cells = <1>;
588 };
589
590 xfi_pll: xfi-pll@11f40000 {
591 compatible = "mediatek,mt7988-xfi-pll", "syscon";
592 reg = <0 0x11f40000 0 0x1000>;
593 #clock-cells = <1>;
594 };
595
596 mcusys: mcusys@100e0000 {
597 compatible = "mediatek,mt7988-mcusys", "syscon";
598 reg = <0 0x100e0000 0 0x1000>;
599 #clock-cells = <1>;
600 };
601
602 uart0: serial@11000000 {
603 compatible = "mediatek,mt7986-uart",
604 "mediatek,mt6577-uart";
605 reg = <0 0x11000000 0 0x100>;
606 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
607 /*
608 * 8250-mtk driver don't control "baud" clock since commit
609 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
610 * still need to be passed to the driver to prevent probe fail
611 */
612 clocks = <&topckgen CLK_TOP_UART_SEL>,
613 <&infracfg CLK_INFRA_52M_UART0_CK>;
614 clock-names = "baud", "bus";
615 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
616 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
617 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
618 <&topckgen CLK_TOP_UART_SEL>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&uart0_pins>;
621 status = "disabled";
622 };
623
624 snand: spi@11001000 {
625 compatible = "mediatek,mt7986-snand";
626 reg = <0 0x11001000 0 0x1000>;
627 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&infracfg CLK_INFRA_SPINFI>,
629 <&infracfg CLK_INFRA_NFI>;
630 clock-names = "pad_clk", "nfi_clk";
631 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
632 <&topckgen CLK_TOP_NFI1X_SEL>;
633 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
634 <&topckgen CLK_TOP_MPLL_D8>;
635 nand-ecc-engine = <&bch>;
636 mediatek,quad-spi;
637 #address-cells = <1>;
638 #size-cells = <0>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&snfi_pins>;
641 status = "disabled";
642 };
643
644 bch: ecc@11002000 {
645 compatible = "mediatek,mt7686-ecc";
646 reg = <0 0x11002000 0 0x1000>;
647 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
649 clock-names = "nfiecc_clk";
650 status = "disabled";
651 };
652
653 i2c0: i2c@11003000 {
654 compatible = "mediatek,mt7988-i2c",
655 "mediatek,mt7981-i2c";
656 reg = <0 0x11003000 0 0x1000>,
657 <0 0x10217080 0 0x80>;
658 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
659 clock-div = <1>;
660 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
661 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
662 clock-names = "main", "dma";
663 #address-cells = <1>;
664 #size-cells = <0>;
665 status = "disabled";
666 };
667
668 i2c1: i2c@11004000 {
669 compatible = "mediatek,mt7988-i2c",
670 "mediatek,mt7981-i2c";
671 reg = <0 0x11004000 0 0x1000>,
672 <0 0x10217100 0 0x80>;
673 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
674 clock-div = <1>;
675 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
676 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
677 clock-names = "main", "dma";
678 #address-cells = <1>;
679 #size-cells = <0>;
680 status = "disabled";
681 };
682
683 i2c2: i2c@11005000 {
684 compatible = "mediatek,mt7988-i2c",
685 "mediatek,mt7981-i2c";
686 reg = <0 0x11005000 0 0x1000>,
687 <0 0x10217180 0 0x80>;
688 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
689 clock-div = <1>;
690 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
691 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
692 clock-names = "main", "dma";
693 #address-cells = <1>;
694 #size-cells = <0>;
695 status = "disabled";
696 };
697
698 spi0: spi@11007000 {
699 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
700 reg = <0 0x11007000 0 0x100>;
701 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&topckgen CLK_TOP_MPLL_D2>,
703 <&topckgen CLK_TOP_SPI_SEL>,
704 <&infracfg CLK_INFRA_104M_SPI0>,
705 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
706 clock-names = "parent-clk", "sel-clk", "spi-clk",
707 "spi-hclk";
708 #address-cells = <1>;
709 #size-cells = <0>;
710 status = "disabled";
711 };
712
713 spi1: spi@11008000 {
714 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
715 reg = <0 0x11008000 0 0x100>;
716 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&topckgen CLK_TOP_MPLL_D2>,
718 <&topckgen CLK_TOP_SPI_SEL>,
719 <&infracfg CLK_INFRA_104M_SPI1>,
720 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
721 clock-names = "parent-clk", "sel-clk", "spi-clk",
722 "spi-hclk";
723 #address-cells = <1>;
724 #size-cells = <0>;
725 pinctrl-names = "default";
726 pinctrl-0 = <&spi1_pins>;
727 status = "disabled";
728 };
729
730 spi2: spi@11009000 {
731 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
732 reg = <0 0x11009000 0 0x100>;
733 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&topckgen CLK_TOP_MPLL_D2>,
735 <&topckgen CLK_TOP_SPI_SEL>,
736 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
737 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
738 clock-names = "parent-clk", "sel-clk", "spi-clk",
739 "spi-hclk";
740 #address-cells = <1>;
741 #size-cells = <0>;
742 status = "disabled";
743 };
744
745 pwm: pwm@10048000 {
746 compatible = "mediatek,mt7988-pwm";
747 reg = <0 0x10048000 0 0x1000>;
748 #pwm-cells = <2>;
749 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
750 <&infracfg CLK_INFRA_66M_PWM_HCK>,
751 <&infracfg CLK_INFRA_66M_PWM_CK1>,
752 <&infracfg CLK_INFRA_66M_PWM_CK2>,
753 <&infracfg CLK_INFRA_66M_PWM_CK3>,
754 <&infracfg CLK_INFRA_66M_PWM_CK4>,
755 <&infracfg CLK_INFRA_66M_PWM_CK5>,
756 <&infracfg CLK_INFRA_66M_PWM_CK6>,
757 <&infracfg CLK_INFRA_66M_PWM_CK7>,
758 <&infracfg CLK_INFRA_66M_PWM_CK8>;
759 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
760 "pwm4","pwm5","pwm6","pwm7","pwm8";
761 status = "disabled";
762 };
763
764 fan: pwm-fan {
765 compatible = "pwm-fan";
766 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
767 cooling-levels = <0 128 255>;
768 #cooling-cells = <2>;
769 #thermal-sensor-cells = <1>;
770 status = "disabled";
771 };
772
773 lvts: lvts@1100a000 {
774 compatible = "mediatek,mt7988-lvts";
775 #thermal-sensor-cells = <1>;
776 reg = <0 0x1100a000 0 0x1000>;
777 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
778 clock-names = "lvts_clk";
779 nvmem-cells = <&lvts_calibration>;
780 nvmem-cell-names = "e_data1";
781 };
782
783 crypto: crypto@15600000 {
784 compatible = "inside-secure,safexcel-eip197b";
785 reg = <0 0x15600000 0 0x180000>;
786 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
790 interrupt-names = "ring0", "ring1", "ring2", "ring3";
791 status = "okay";
792 };
793
794 afe: audio-controller@11210000 {
795 compatible = "mediatek,mt79xx-audio";
796 reg = <0 0x11210000 0 0x9000>;
797 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
799 <&infracfg CLK_INFRA_AUD_26M>,
800 <&infracfg CLK_INFRA_AUD_L>,
801 <&infracfg CLK_INFRA_AUD_AUD>,
802 <&infracfg CLK_INFRA_AUD_EG2>,
803 <&topckgen CLK_TOP_AUD_SEL>,
804 <&topckgen CLK_TOP_AUD_I2S_M>;
805 clock-names = "aud_bus_ck",
806 "aud_26m_ck",
807 "aud_l_ck",
808 "aud_aud_ck",
809 "aud_eg2_ck",
810 "aud_sel",
811 "aud_i2s_m";
812 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
813 <&topckgen CLK_TOP_A1SYS_SEL>,
814 <&topckgen CLK_TOP_AUD_L_SEL>,
815 <&topckgen CLK_TOP_A_TUNER_SEL>;
816 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
817 <&topckgen CLK_TOP_APLL2_D4>,
818 <&apmixedsys CLK_APMIXED_APLL2>,
819 <&topckgen CLK_TOP_APLL2_D4>;
820 status = "disabled";
821 };
822
823 pcie2: pcie@11280000 {
824 compatible = "mediatek,mt7988-pcie",
825 "mediatek,mt7986-pcie",
826 "mediatek,mt8192-pcie";
827 device_type = "pci";
828 #address-cells = <3>;
829 #size-cells = <2>;
830 reg = <0 0x11280000 0 0x2000>;
831 reg-names = "pcie-mac";
832 linux,pci-domain = <3>;
833 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
834 bus-range = <0x00 0xff>;
835 ranges = <0x81000000 0x00 0x20000000 0x00
836 0x20000000 0x00 0x00200000>,
837 <0x82000000 0x00 0x20200000 0x00
838 0x20200000 0x00 0x07e00000>;
839 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
840 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
841 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
842 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
843 clock-names = "pl_250m", "tl_26m", "peri_26m",
844 "top_133m";
845 pinctrl-names = "default";
846 pinctrl-0 = <&pcie2_pins>;
847 status = "disabled";
848
849 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
850 phy-names = "pcie-phy";
851
852 #interrupt-cells = <1>;
853 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
855 <0 0 0 2 &pcie_intc2 1>,
856 <0 0 0 3 &pcie_intc2 2>,
857 <0 0 0 4 &pcie_intc2 3>;
858 pcie_intc2: interrupt-controller {
859 #address-cells = <0>;
860 #interrupt-cells = <1>;
861 interrupt-controller;
862 };
863 };
864
865 pcie3: pcie@11290000 {
866 compatible = "mediatek,mt7988-pcie",
867 "mediatek,mt7986-pcie",
868 "mediatek,mt8192-pcie";
869 device_type = "pci";
870 #address-cells = <3>;
871 #size-cells = <2>;
872 reg = <0 0x11290000 0 0x2000>;
873 reg-names = "pcie-mac";
874 linux,pci-domain = <2>;
875 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
876 bus-range = <0x00 0xff>;
877 ranges = <0x81000000 0x00 0x28000000 0x00
878 0x28000000 0x00 0x00200000>,
879 <0x82000000 0x00 0x28200000 0x00
880 0x28200000 0x00 0x07e00000>;
881 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
882 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
883 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
884 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
885 clock-names = "pl_250m", "tl_26m", "peri_26m",
886 "top_133m";
887 pinctrl-names = "default";
888 pinctrl-0 = <&pcie3_pins>;
889 status = "disabled";
890
891 #interrupt-cells = <1>;
892 interrupt-map-mask = <0 0 0 0x7>;
893 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
894 <0 0 0 2 &pcie_intc3 1>,
895 <0 0 0 3 &pcie_intc3 2>,
896 <0 0 0 4 &pcie_intc3 3>;
897 pcie_intc3: interrupt-controller {
898 #address-cells = <0>;
899 #interrupt-cells = <1>;
900 interrupt-controller;
901 };
902 };
903
904 pcie0: pcie@11300000 {
905 compatible = "mediatek,mt7988-pcie",
906 "mediatek,mt7986-pcie",
907 "mediatek,mt8192-pcie";
908 device_type = "pci";
909 #address-cells = <3>;
910 #size-cells = <2>;
911 reg = <0 0x11300000 0 0x2000>;
912 reg-names = "pcie-mac";
913 linux,pci-domain = <0>;
914 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
915 bus-range = <0x00 0xff>;
916 ranges = <0x81000000 0x00 0x30000000 0x00
917 0x30000000 0x00 0x00200000>,
918 <0x82000000 0x00 0x30200000 0x00
919 0x30200000 0x00 0x07e00000>;
920 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
921 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
922 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
923 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
924 clock-names = "pl_250m", "tl_26m", "peri_26m",
925 "top_133m";
926 pinctrl-names = "default";
927 pinctrl-0 = <&pcie0_pins>;
928 status = "disabled";
929
930 #interrupt-cells = <1>;
931 interrupt-map-mask = <0 0 0 0x7>;
932 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
933 <0 0 0 2 &pcie_intc0 1>,
934 <0 0 0 3 &pcie_intc0 2>,
935 <0 0 0 4 &pcie_intc0 3>;
936 pcie_intc0: interrupt-controller {
937 #address-cells = <0>;
938 #interrupt-cells = <1>;
939 interrupt-controller;
940 };
941 };
942
943 pcie1: pcie@11310000 {
944 compatible = "mediatek,mt7988-pcie",
945 "mediatek,mt7986-pcie",
946 "mediatek,mt8192-pcie";
947 device_type = "pci";
948 #address-cells = <3>;
949 #size-cells = <2>;
950 reg = <0 0x11310000 0 0x2000>;
951 reg-names = "pcie-mac";
952 linux,pci-domain = <1>;
953 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
954 bus-range = <0x00 0xff>;
955 ranges = <0x81000000 0x00 0x38000000 0x00
956 0x38000000 0x00 0x00200000>,
957 <0x82000000 0x00 0x38200000 0x00
958 0x38200000 0x00 0x07e00000>;
959 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
960 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
961 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
962 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
963 clock-names = "pl_250m", "tl_26m", "peri_26m",
964 "top_133m";
965 pinctrl-names = "default";
966 pinctrl-0 = <&pcie1_pins>;
967 status = "disabled";
968
969 #interrupt-cells = <1>;
970 interrupt-map-mask = <0 0 0 0x7>;
971 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
972 <0 0 0 2 &pcie_intc1 1>,
973 <0 0 0 3 &pcie_intc1 2>,
974 <0 0 0 4 &pcie_intc1 3>;
975 pcie_intc1: interrupt-controller {
976 #address-cells = <0>;
977 #interrupt-cells = <1>;
978 interrupt-controller;
979 };
980 };
981
982 ssusb0: usb@11190000 {
983 compatible = "mediatek,mt7988-xhci",
984 "mediatek,mtk-xhci";
985 reg = <0 0x11190000 0 0x2e00>,
986 <0 0x11193e00 0 0x0100>;
987 reg-names = "mac", "ippc";
988 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
989 phys = <&xphyu2port0 PHY_TYPE_USB2>,
990 <&xphyu3port0 PHY_TYPE_USB3>;
991 clocks = <&infracfg CLK_INFRA_USB_SYS>,
992 <&infracfg CLK_INFRA_USB_XHCI>,
993 <&infracfg CLK_INFRA_USB_REF>,
994 <&infracfg CLK_INFRA_66M_USB_HCK>,
995 <&infracfg CLK_INFRA_133M_USB_HCK>;
996 clock-names = "sys_ck",
997 "xhci_ck",
998 "ref_ck",
999 "mcu_ck",
1000 "dma_ck";
1001 #address-cells = <2>;
1002 #size-cells = <2>;
1003 mediatek,p0_speed_fixup;
1004 status = "disabled";
1005 };
1006
1007 ssusb1: usb@11200000 {
1008 compatible = "mediatek,mt7988-xhci",
1009 "mediatek,mtk-xhci";
1010 reg = <0 0x11200000 0 0x2e00>,
1011 <0 0x11203e00 0 0x0100>;
1012 reg-names = "mac", "ippc";
1013 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1014 phys = <&tphyu2port0 PHY_TYPE_USB2>,
1015 <&tphyu3port0 PHY_TYPE_USB3>;
1016 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
1017 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
1018 <&infracfg CLK_INFRA_USB_CK_P1>,
1019 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
1020 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
1021 clock-names = "sys_ck",
1022 "xhci_ck",
1023 "ref_ck",
1024 "mcu_ck",
1025 "dma_ck";
1026 #address-cells = <2>;
1027 #size-cells = <2>;
1028 status = "disabled";
1029 };
1030
1031 mmc0: mmc@11230000 {
1032 compatible = "mediatek,mt7986-mmc",
1033 "mediatek,mt7981-mmc";
1034 reg = <0 0x11230000 0 0x1000>,
1035 <0 0x11D60000 0 0x1000>;
1036 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&infracfg CLK_INFRA_MSDC400>,
1038 <&infracfg CLK_INFRA_MSDC2_HCK>,
1039 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
1040 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
1041 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
1042 <&topckgen CLK_TOP_EMMC_400M_SEL>;
1043 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
1044 <&apmixedsys CLK_APMIXED_MSDCPLL>;
1045 clock-names = "source",
1046 "hclk",
1047 "axi_cg",
1048 "ahb_cg";
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051 status = "disabled";
1052 };
1053
1054 tphy: tphy@11c50000 {
1055 compatible = "mediatek,mt7988",
1056 "mediatek,generic-tphy-v2";
1057 #address-cells = <2>;
1058 #size-cells = <2>;
1059 ranges;
1060 status = "disabled";
1061 tphyu2port0: usb-phy@11c50000 {
1062 reg = <0 0x11c50000 0 0x700>;
1063 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
1064 clock-names = "ref";
1065 #phy-cells = <1>;
1066 };
1067 tphyu3port0: usb-phy@11c50700 {
1068 reg = <0 0x11c50700 0 0x900>;
1069 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
1070 clock-names = "ref";
1071 #phy-cells = <1>;
1072 mediatek,usb3-pll-ssc-delta;
1073 mediatek,usb3-pll-ssc-delta1;
1074 };
1075 };
1076
1077 topmisc: topmisc@11d10000 {
1078 compatible = "mediatek,mt7988-topmisc", "syscon",
1079 "mediatek,mt7988-power-controller";
1080 reg = <0 0x11d10000 0 0x10000>;
1081 #clock-cells = <1>;
1082 #power-domain-cells = <1>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 };
1086
1087 xphy: xphy@11e10000 {
1088 compatible = "mediatek,mt7988",
1089 "mediatek,xsphy";
1090 #address-cells = <2>;
1091 #size-cells = <2>;
1092 ranges;
1093 status = "disabled";
1094
1095 xphyu2port0: usb-phy@11e10000 {
1096 reg = <0 0x11e10000 0 0x400>;
1097 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1098 clock-names = "ref";
1099 #phy-cells = <1>;
1100 };
1101
1102 xphyu3port0: usb-phy@11e13000 {
1103 reg = <0 0x11e13400 0 0x500>;
1104 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1105 clock-names = "ref";
1106 #phy-cells = <1>;
1107 mediatek,syscon-type = <&topmisc 0x218 0>;
1108 };
1109 };
1110
1111 efuse: efuse@11f50000 {
1112 compatible = "mediatek,efuse";
1113 reg = <0 0x11f50000 0 0x1000>;
1114 #address-cells = <1>;
1115 #size-cells = <1>;
1116
1117 lvts_calibration: calib@918 {
1118 reg = <0x918 0x28>;
1119 };
1120 phy_calibration_p0: calib@940 {
1121 reg = <0x940 0x10>;
1122 };
1123 phy_calibration_p1: calib@954 {
1124 reg = <0x954 0x10>;
1125 };
1126 phy_calibration_p2: calib@968 {
1127 reg = <0x968 0x10>;
1128 };
1129 phy_calibration_p3: calib@97c {
1130 reg = <0x97c 0x10>;
1131 };
1132 cpufreq_calibration: calib@278 {
1133 reg = <0x278 0x1>;
1134 };
1135 };
1136
1137 ethsys: syscon@15000000 {
1138 #address-cells = <1>;
1139 #size-cells = <1>;
1140 compatible = "mediatek,mt7988-ethsys", "syscon";
1141 reg = <0 0x15000000 0 0x1000>;
1142 #clock-cells = <1>;
1143 #reset-cells = <1>;
1144 };
1145
1146 switch: switch@15020000 {
1147 #address-cells = <1>;
1148 #size-cells = <1>;
1149 compatible = "mediatek,mt7988-switch";
1150 reg = <0 0x15020000 0 0x8000>;
1151 interrupt-controller;
1152 #interrupt-cells = <1>;
1153 interrupt-parent = <&gic>;
1154 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1155 resets = <&ethrst 0>;
1156
1157 ports {
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160
1161 port@0 {
1162 reg = <0>;
1163 label = "lan0";
1164 phy-mode = "internal";
1165 phy-handle = <&gsw_phy0>;
1166 };
1167
1168 port@1 {
1169 reg = <1>;
1170 label = "lan1";
1171 phy-mode = "internal";
1172 phy-handle = <&gsw_phy1>;
1173 };
1174
1175 port@2 {
1176 reg = <2>;
1177 label = "lan2";
1178 phy-mode = "internal";
1179 phy-handle = <&gsw_phy2>;
1180 };
1181
1182 port@3 {
1183 reg = <3>;
1184 label = "lan3";
1185 phy-mode = "internal";
1186 phy-handle = <&gsw_phy3>;
1187 };
1188
1189 port@6 {
1190 reg = <6>;
1191 ethernet = <&gmac0>;
1192 phy-mode = "internal";
1193
1194 fixed-link {
1195 speed = <10000>;
1196 full-duplex;
1197 pause;
1198 };
1199 };
1200 };
1201
1202 mdio {
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1205 mediatek,pio = <&pio>;
1206
1207 gsw_phy0: ethernet-phy@0 {
1208 compatible = "ethernet-phy-ieee802.3-c22";
1209 reg = <0>;
1210 phy-mode = "internal";
1211 nvmem-cells = <&phy_calibration_p0>;
1212 nvmem-cell-names = "phy-cal-data";
1213
1214 leds {
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217
1218 gsw_phy0_led0: gsw-phy0-led0@0 {
1219 reg = <0>;
1220 function = LED_FUNCTION_LAN;
1221 status = "disabled";
1222 };
1223
1224 gsw_phy0_led1: gsw-phy0-led1@1 {
1225 reg = <1>;
1226 function = LED_FUNCTION_LAN;
1227 status = "disabled";
1228 };
1229 };
1230 };
1231
1232 gsw_phy1: ethernet-phy@1 {
1233 compatible = "ethernet-phy-ieee802.3-c22";
1234 reg = <1>;
1235 phy-mode = "internal";
1236 nvmem-cells = <&phy_calibration_p1>;
1237 nvmem-cell-names = "phy-cal-data";
1238
1239 leds {
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1242
1243 gsw_phy1_led0: gsw-phy1-led0@0 {
1244 reg = <0>;
1245 function = LED_FUNCTION_LAN;
1246 status = "disabled";
1247 };
1248
1249 gsw_phy1_led1: gsw-phy1-led1@1 {
1250 reg = <1>;
1251 function = LED_FUNCTION_LAN;
1252 status = "disabled";
1253 };
1254 };
1255 };
1256
1257 gsw_phy2: ethernet-phy@2 {
1258 compatible = "ethernet-phy-ieee802.3-c22";
1259 reg = <2>;
1260 phy-mode = "internal";
1261 nvmem-cells = <&phy_calibration_p2>;
1262 nvmem-cell-names = "phy-cal-data";
1263
1264 leds {
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1267
1268 gsw_phy2_led0: gsw-phy2-led0@0 {
1269 reg = <0>;
1270 function = LED_FUNCTION_LAN;
1271 status = "disabled";
1272 };
1273
1274 gsw_phy2_led1: gsw-phy2-led1@1 {
1275 reg = <1>;
1276 function = LED_FUNCTION_LAN;
1277 status = "disabled";
1278 };
1279 };
1280 };
1281
1282 gsw_phy3: ethernet-phy@3 {
1283 compatible = "ethernet-phy-ieee802.3-c22";
1284 reg = <3>;
1285 phy-mode = "internal";
1286 nvmem-cells = <&phy_calibration_p3>;
1287 nvmem-cell-names = "phy-cal-data";
1288
1289 leds {
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1292
1293 gsw_phy3_led0: gsw-phy3-led0@0 {
1294 reg = <0>;
1295 function = LED_FUNCTION_LAN;
1296 status = "disabled";
1297 };
1298
1299 gsw_phy3_led1: gsw-phy3-led1@1 {
1300 reg = <1>;
1301 function = LED_FUNCTION_LAN;
1302 status = "disabled";
1303 };
1304 };
1305 };
1306 };
1307 };
1308
1309 ethwarp: syscon@15031000 {
1310 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
1311 reg = <0 0x15031000 0 0x1000>;
1312 #clock-cells = <1>;
1313
1314 ethrst: reset-controller {
1315 compatible = "ti,syscon-reset";
1316 #reset-cells = <1>;
1317 ti,reset-bits = <
1318 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
1319 >;
1320 };
1321 };
1322
1323 eth: ethernet@15100000 {
1324 compatible = "mediatek,mt7988-eth";
1325 reg = <0 0x15100000 0 0x80000>,
1326 <0 0x15400000 0 0x380000>;
1327 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1332 <&ethsys CLK_ETHDMA_XGP2_EN>,
1333 <&ethsys CLK_ETHDMA_XGP3_EN>,
1334 <&ethsys CLK_ETHDMA_FE_EN>,
1335 <&ethsys CLK_ETHDMA_GP2_EN>,
1336 <&ethsys CLK_ETHDMA_GP1_EN>,
1337 <&ethsys CLK_ETHDMA_GP3_EN>,
1338 <&ethsys CLK_ETHDMA_ESW_EN>,
1339 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1340 <&sgmiisys0 CLK_SGM0_TX_EN>,
1341 <&sgmiisys0 CLK_SGM0_RX_EN>,
1342 <&sgmiisys1 CLK_SGM1_TX_EN>,
1343 <&sgmiisys1 CLK_SGM1_RX_EN>,
1344 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1345 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1346 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1347 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1348 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1349 <&topckgen CLK_TOP_SGM_0_SEL>,
1350 <&topckgen CLK_TOP_SGM_1_SEL>,
1351 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
1352 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
1353 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1354 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1355 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1356 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1357 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1358 <&topckgen CLK_TOP_ETH_MII_SEL>,
1359 <&topckgen CLK_TOP_NETSYS_SEL>,
1360 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1361 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1362 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1363 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1364 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1365 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1366 "gp3", "esw", "crypto", "sgmii_tx250m",
1367 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
1368 "ethwarp_wocpu2", "ethwarp_wocpu1",
1369 "ethwarp_wocpu0", "top_usxgmii0_sel",
1370 "top_usxgmii1_sel", "top_sgm0_sel",
1371 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
1372 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
1373 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1374 "top_eth_sys_sel", "top_eth_xgmii_sel",
1375 "top_eth_mii_sel", "top_netsys_sel",
1376 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1377 "top_netsys_sync_250m_sel",
1378 "top_netsys_ppefb_250m_sel",
1379 "top_netsys_warp_sel";
1380 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1381 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1382 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1383 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1384 <&topckgen CLK_TOP_SGM_0_SEL>,
1385 <&topckgen CLK_TOP_SGM_1_SEL>;
1386 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1387 <&topckgen CLK_TOP_NET1PLL_D4>,
1388 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1389 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1390 <&apmixedsys CLK_APMIXED_SGMPLL>,
1391 <&apmixedsys CLK_APMIXED_SGMPLL>;
1392 mediatek,ethsys = <&ethsys>;
1393 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
1394 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
1395 mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
1396 mediatek,xfi-pll = <&xfi_pll>;
1397 mediatek,infracfg = <&topmisc>;
1398 mediatek,toprgu = <&watchdog>;
1399 #reset-cells = <1>;
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1402
1403 gmac0: mac@0 {
1404 compatible = "mediatek,eth-mac";
1405 reg = <0>;
1406 phy-mode = "internal";
1407 status = "disabled";
1408
1409 fixed-link {
1410 speed = <10000>;
1411 full-duplex;
1412 pause;
1413 };
1414 };
1415
1416 gmac1: mac@1 {
1417 compatible = "mediatek,eth-mac";
1418 reg = <1>;
1419 status = "disabled";
1420 };
1421
1422 gmac2: mac@2 {
1423 compatible = "mediatek,eth-mac";
1424 reg = <2>;
1425 status = "disabled";
1426 };
1427
1428 mdio_bus: mdio-bus {
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1431
1432 /* internal 2.5G PHY */
1433 int_2p5g_phy: ethernet-phy@15 {
1434 reg = <15>;
1435 compatible = "ethernet-phy-ieee802.3-c45";
1436 phy-mode = "internal";
1437 };
1438 };
1439 };
1440 };
1441 };
Staging tree of Stijn Tintel